Split gate flash cell semiconductor device

Abstract

A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.

What is claimed is: 
     
       1. A floating gate transistor comprising:
 a floating gate transistor substructure including an oxide disposed on a silicon gate disposed over a gate oxide disposed on a substrate, said oxide having a maximum width less than a width of said silicon gate and said silicon gate including a concave upper surface; 
 an inter-gate dielectric disposed over said floating gate transistor substructure including over said oxide, and directly contacting portions of said concave upper surface; and 
 a silicon layer with a lower surface disposed over said inter-gate dielectric and said silicon gate, said lower surface facing said silicon gate and including both concave and convex portions overlying an uppermost surface of said floating gate transistor substructure. 
 
     
     
       2. The floating gate transistor as in  claim 1 , wherein said silicon layer comprises a control gate and said lower surface is conterminous with portions of said inter-gate dielectric. 
     
     
       3. The floating gate transistor as in  claim 2 , wherein said control gate includes an inwardly extending notch at a location where said control gate extends over an upper edge of said silicon gate. 
     
     
       4. The floating gate transistor as in  claim 2 , wherein said control gate extends over only a portion of said floating gate transistor substructure and also extends along a sidewall thereof. 
     
     
       5. The floating gate transistor as in  claim 1 , wherein said inter-gate dielectric is in direct contact with said oxide. 
     
     
       6. The floating gate transistor as in  claim 1 , further comprising spacers directly covering respective end portions of said gate oxide that terminate at said sidewalls. 
     
     
       7. The floating gate transistor as in  claim 6 , wherein said spacers are composite structures including a nitride layer disposed between two oxide layers. 
     
     
       8. The floating gate transistor as in  claim 1 , further comprising a further floating gate transistor substructure that shares a common source area formed in a substrate, with said floating gate transistor substructure. 
     
     
       9. The floating gate transistor as in  claim 1 , wherein said oxide is conterminous with said concave upper surface. 
     
     
       10. The floating gate transistor as in  claim 1 , wherein said oxide is bi-convex in shape and includes a centrally located maximum thickness portion and a duality of opposed lateral ends that substantially form vertices. 
     
     
       11. The floating gate transistor as in  claim 10 , further comprising a silicide layer on said silicon layer. 
     
     
       12. The floating gate transistor as in  claim 1 , further comprising a silicide layer on said silicon layer. 
     
     
       13. The floating gate transistor as in  claim 1 , wherein said lower surface is conterminous with portions of said inter-gate dielectric and said silicon layer includes an inwardly extending notch at a location where said silicon layer extends over an upper edge of said silicon gate. 
     
     
       14. The floating gate transistor as in  claim 1 , wherein said silicon layer comprises a control gate that extends over only a portion of said floating gate transistor substructure and also extends along a sidewall thereof. 
     
     
       15. A split gate flash cell semiconductor device comprising:
 a duality of floating gate transistors sharing a common source area formed in a substrate, each said floating gate transistor comprising: 
 a floating gate transistor substructure including an oxide disposed on a silicon gate disposed over a gate oxide disposed on a substrate, said oxide having a maximum width less than a width of said silicon gate and said silicon gate including a concave upper surface; 
 an inter-gate dielectric disposed over said floating gate transistor substructure including over said oxide, and directly contacting portions of said concave upper surface; and 
 a silicon layer with a lower surface disposed over said inter-gate dielectric and said silicon gate, said lower surface facing said silicon gate and including both concave and convex portions overlying an uppermost surface of said floating gate transistor substructure. 
 
     
     
       16. The split gate flash cell semiconductor device as in  claim 15 , wherein said oxide is bi-convex in shape and includes a centrally located maximum thickness portion and a duality of opposed lateral ends that substantially form vertices. 
     
     
       17. The split gate flash cell semiconductor device as in  claim 16 , further comprising a silicide layer on said silicon layer. 
     
     
       18. The split gate flash cell semiconductor device as in  claim 15 , further comprising a silicide layer on said silicon layer. 
     
     
       19. The split gate flash cell semiconductor device as in  claim 15 , wherein said lower surface includes an inwardly extending notch at a location where said silicon layer extends over an upper edge of said silicon gate.