Latch-based memory array

Abstract

The invention concerns a memory array having memory cells arranged in columns and rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells includes a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between the first storage node and a first test data input; and a second transistor coupled between the second storage node and a second test data input.

The invention claimed is: 
     
       1. A memory array comprising memory cells arranged in a plurality of columns and in a plurality of rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, each of the memory cells having:
 a latch formed of a pair of inverters cross-coupled between first and second storage nodes; 
 a first transistor coupled between said first storage node and a first test data input; and 
 a second transistor coupled between said second storage node and a second test data input; 
 wherein a first of said memory cells has its first and second test data inputs coupled to test sequence input circuitry, and wherein a second of said memory cells has its first test data input coupled to the first storage node of said first memory cell via a first buffer of said first memory cell and its second test data input coupled to the second storage node of said first memory cell via a second buffer of said first memory cell. 
 
     
     
       2. The memory array of  claim 1 , wherein each memory cell further comprises a data output, each of the data outputs being independently connected to an output port of said memory array. 
     
     
       3. The memory array of  claim 2 , wherein said first buffer provides said data output and comprises a third transistor coupling said data output to a first supply voltage and a fourth transistor coupling said data output to a second supply voltage, the third and fourth transistors having their control nodes coupled to said first or second storage node. 
     
     
       4. The memory array of  claim 1 , wherein said first and second transistors of said first memory cell are configured to receive a clock signal, and wherein said first and second transistors of said second memory cell are configured to receive the inverse of said clock signal. 
     
     
       5. The memory array of  claim 4 , wherein the memory cells of said array are coupled in series by their test data inputs and data outputs to form a test chain, and wherein said first memory cell and alternate memory cells thereafter of said test chain receive said clock signal on a first clock line, and wherein the other memory cells of said test chain receive the inverse of said clock signal on a second clock line. 
     
     
       6. The memory array of  claim 1 , wherein:
 said first and second memory cells are arranged in a first column of said memory array, said first memory cell being at one end of said first column at a first side of said memory array, and a final memory cell being at the other end of said first column at a second side of said memory array; 
 the memory array comprises a second column adjacent to said first column, another first memory cell being at one end of said second column at said first side of the memory array and a another final memory cell being at the other end of said second column at said second side of the memory array; 
 a first test data input of said final memory cell of said second column is coupled to the first storage node of said final memory cell of said first column via said first buffer; and 
 a second test data input of said final memory cell of said second column is coupled to the second storage node of said final memory cell of said first column via said second buffer. 
 
     
     
       7. The memory array of  claim 1 , wherein said at least one common write line comprises a first common write line and a second common write line. 
     
     
       8. The memory array of  claim 7 , wherein each of said memory cells further comprises a fifth transistor coupled between said first storage node and a first supply voltage, and a sixth transistor coupled between said second storage node and said first supply voltage, the control node of said fifth transistor being coupled to said first common write line, and the control node of said sixth transistor being coupled to said second common write line. 
     
     
       9. The memory array of  claim 8 , wherein each memory cell further comprises a seventh transistor coupled between said first storage node and said first supply voltage in series with said fifth transistor, and an eighth transistor coupled between said second storage node and said first supply voltage in series with said sixth transistor, wherein control nodes of said seventh and eighth transistors are coupled to the common selection line of the row. 
     
     
       10. The memory array of  claim 1 , wherein said first and second inverters each comprises first and second p-channel MOS transistors coupled in series with an n-channel MOS transistor between first and second supply voltages. 
     
     
       11. A method of testing a memory array comprising memory cells arranged in a plurality of columns and in a plurality of rows, the memory cells of each column being coupled to at least one common write line of their column, the memory cells of each row being coupled to a common selection line of their row, wherein each of the memory cells comprises a latch formed of a pair of inverters cross-coupled between first and second storage nodes; a first transistor coupled between said first storage node and a first test data input; and a second transistor coupled between said second storage node and a second test data input, a first of said memory cells having its first and second test data inputs coupled to test sequence input circuitry, and a second of said memory cells having its first test data input coupled to the first storage node of said first memory cell via a first buffer of said first memory cell and its second test data input coupled to the second storage node of said first memory cell via a second buffer of said first memory cell, the method comprising:
 applying a first test signal to said first test data input and a second test signal to said second test data input; and activating said first and second transistors such that said first test signal is applied to said first storage node and said second test signal is applied to said second storage node.