Efficient generation of spreading sequence correlations using lookup tables

Abstract

A signal is received containing a block of multiple symbols, each symbol containing information bits spread by a spreading sequence of chips. Each spreading sequence is determined by a channelization sequence and a first or second complex-valued scrambling sequence of chips. Each block is processed using a set of spreading sequences using correlations between pairs of spreading sequences in the set. Spreading sequence correlation values between each pair are manipulated and stored in lookup tables. A lookup table address is determined using a first set of reduced basic scrambling bits to retrieve correlation values. The first set of reduced basic scrambling bits is based on manipulation of one set of the basic scrambling bits that reduces a number of bits included in the determined address to less than a number of binary values in the one set of basic scrambling bits. The one set of basic scrambling bits is used to construct one of the first and second complex-valued scrambling sequences. The retrieved correlation values may be used in mitigating spreading sequence correlation interference between spreading sequences in the set.

The invention claimed is: 
     
       1. A method in a receiver, comprising:
 receiving a signal containing a block of multiple symbols, each symbol containing information bits spread by a spreading sequence of chips, where each spreading sequence is determined by a channelization sequence and a first complex-valued scrambling sequence of chips or a second complex-valued scrambling sequence of chips; 
 processing each symbol block using a set of multiple spreading sequences using one or more correlations between one or more pairs of spreading sequences in the set, wherein spreading sequence correlation values between each pair of the multiple spreading sequences in the set are manipulated and stored in one or more lookup tables; 
 addressing one of the lookup tables with an address determined using a first set of reduced basic scrambling bits to retrieve one or more correlation values from the addressed lookup table, wherein the first set of reduced basic scrambling bits is based on manipulation of one set of basic scrambling bits which reduces a number of bits included in the determined address to less than a number of binary values in the one set of basic scrambling bits, wherein the one set of basic scrambling bits is used to construct one of the first and second complex-valued scrambling sequences; and 
 using the retrieved one or more correlation values in mitigating spreading sequence correlation interference between spreading sequences in the set in a process to detect symbol values for two or more information symbols in the symbol block. 
 
     
     
       2. The method in  claim 1 , wherein manipulation of the one set of basic scrambling bits includes exploiting one or more redundancies of the one set of basic scrambling bits. 
     
     
       3. The method in  claim 2 , wherein the manipulation includes eliminating at least one bit in the one set of basic scrambling bits for addressing the one lookup table based on a redundant bit value in the one set of basic scrambling bits. 
     
     
       4. The method in  claim 2 , wherein the manipulation includes storing only a correlation value for two different correlations between each pair of the multiple spreading sequences. 
     
     
       5. The method in  claim 4 , wherein the first set of address bits represents a number that is smaller than or equal to the number represented by the second set of address bits. 
     
     
       6. The method of  claim 4 , wherein the first set of address bits represents a number that is greater than the number represented by the second set of address bits, exchanging values of the first and the second sets address bits to compute the address value, and changing the sign of the time lag to find the address in one of the lookup tables. 
     
     
       7. The method in  claim 2 , wherein the manipulation includes storing entries in the lookup table only where a first bit in each of two of the first set of scrambling generation bits is equal to 0 in a 0/1 representation of binary bits. 
     
     
       8. The method in  claim 7 , wherein the address bits used to access the lookup table do not contain the first bit. 
     
     
       9. The method in  claim 1 , wherein each complex-valued scrambling sequence is determined by a first binary-valued scrambling sequence that determines a real part of the complex-valued scrambling sequence and a second binary-valued scrambling sequence that determines an imaginary part of the complex-valued scrambling sequence. 
     
     
       10. The method in  claim 9 , further comprising:
 generating the first and second binary-valued scrambling sequences for the first complex-valued scrambling sequence, and 
 determining the first set of the reduced basic scrambling bits based on the first and second binary-valued scrambling sequences for the first complex-valued scrambling sequence. 
 
     
     
       11. The method in  claim 10 , wherein the address includes a first set of address bits and a second set of address bits, the method further comprising:
 generating the first and second binary-valued scrambling sequences for the second complex-valued scrambling sequence; 
 determining a second set of reduced basic scrambling bits based on the first and second binary-valued scrambling sequences for the second complex-valued scrambling sequence; and 
 determining the second set of address bits based on the second set of the reduced basic scrambling bits, 
 wherein the one lookup table is addressed with an address determined using the first set of address bits and the second set of address bits to retrieve a first set of correlation values associated with the spreading sequences of the two or more information symbols. 
 
     
     
       12. The method in  claim 11 , further comprising:
 mapping the first set of correlation values to an actual correlation value. 
 
     
     
       13. The method in  claim 11 , wherein determining the first set of address bits includes performing an exclusive-OR (XOR) product operation with an anchor bit among the first set of the reduced basic scrambling bits and with each of the other bits among the first set of the reduced basic scrambling bits, and forming the first set of address bits based on the XOR products. 
     
     
       14. The method of  claim 1 , wherein the complex-valued scrambling sequence is defined by:
     C   long,n ( i )= c   long,1,n ( i )(1+ j (−1) i   c   long,2,n (2 └i/ 2┘))
 
 wherein: 
 i is a chip index starting at 0, 
 the block is a 4-chip symbol block, 
 the binary values of the scrambling sequence are eight binary values based on the binary values c long,1,n (0), c long,2,n  (0), c long,1,n (1), c long,2,n (1), c long,1,n  (2), c long,2,n (2), c long,1,n (3), c long,2,n (3) and correspond to the one set of basic scrambling bits, and 
 c long,1,n (0), c long,2,n  (0), c long,1,n (1), c long,1,n  (2), c long,2,n (2), c long,1,n (3) correspond to the reduced basic scrambling bits. 
 
     
     
       15. An apparatus for a receiver, comprising:
 a receiver configured to receive a signal containing a block of multiple symbols, each symbol containing information bits spread by a spreading sequence of chips, where each spreading sequence is determined by a channelization sequence and a first complex-valued scrambling sequence of chips or a second complex-valued scrambling sequence of chips; 
 correlation circuitry configured to process each block using a set of multiple spreading sequences using one or more correlations between one or more pairs of spreading sequences in the set, wherein spreading sequence correlation values between each pair of the multiple spreading sequences in the set are manipulated and stored in one or more lookup tables; 
 an address generator configured to address one of the lookup tables with an address determined using a first set of reduced basic scrambling bits to retrieve one or more correlation values from the addressed lookup table, wherein the first set of reduced basic scrambling bits is used to construct one of the first and second complex-valued scrambling sequences and is based on manipulation of the one set of basic scrambling bits which reduces a number of bits included in the determined address to less than a number of binary values in the one set of basic scrambling bits; and 
 symbol estimation circuitry configured to use the retrieved one or more correlation values in mitigating spreading sequence correlation interference between spreading sequences in the set in a process to detect symbol values for two or more information symbols in the received block. 
 
     
     
       16. The apparatus in  claim 15 , wherein manipulation of the one scrambling sequence includes exploiting one or more redundancies of the one scrambling sequence. 
     
     
       17. The apparatus in  claim 16 , wherein the manipulation includes eliminating at least one bit in the one scrambling sequence for addressing the one lookup table based on a redundant bit value in the one scrambling sequence. 
     
     
       18. The apparatus in  claim 16 , wherein the manipulation includes storing only a correlation value for two different correlations between each pair of the multiple spreading sequences. 
     
     
       19. The apparatus in  claim 18 , wherein the first set of address bits represents a number that is smaller than or equal to the number represented by the second set of address bits. 
     
     
       20. The apparatus of  claim 18 , wherein the first set of address bits represents a number that is greater than the number represented by the second set of address bits, exchanging values of the first and the second sets address bits to compute the address value, and changing the sign of the time lag to find the address in one of the lookup tables. 
     
     
       21. The apparatus in  claim 16 , wherein the manipulation includes storing entries in the lookup table only where a first bit in each of two of the first set of scrambling generation bits is equal to 0. 
     
     
       22. The apparatus in  claim 15 , wherein each complex-valued scrambling sequence is determined by a first binary-valued scrambling sequence that determines a real part of the complex-valued scrambling sequence and a second binary-valued scrambling sequence that determines an imaginary part of the complex-valued scrambling sequence. 
     
     
       23. The apparatus in  claim 22 , wherein the address bits used to access the lookup table do not contain the first bit. 
     
     
       24. The apparatus in  claim 23 , further comprising:
 a code generator configured to generate the first and second binary-valued scrambling sequences for the first complex-valued scrambling sequence, and 
 a scrambling bits processor configured to determine the first set of the scrambling generation bits based on the first and second binary-valued scrambling sequences for the first complex-valued scrambling sequence. 
 
     
     
       25. The apparatus in  claim 24 , wherein the address includes a first set of address bits and a second set of address bits, the apparatus further comprising:
 a code generator configured to generate the first and second binary-valued scrambling sequences for the second complex-valued scrambling sequence; 
 a scrambling bits processor configured to determine a second set of scrambling generation bits based on the first and second binary-valued scrambling sequences for the second complex-valued scrambling sequence; 
 determining the second set of address bits based on the second set of the scrambling generation bits; and 
 wherein the one lookup table is addressed with an address determined using the first set of address bits and the second set of address bits to retrieve a first set of correlation values associated with the spreading sequences of the two or more information symbols. 
 
     
     
       26. The apparatus in  claim 25 , further comprising:
 mapping circuitry configured to map the first set of correlation values to an actual correlation value. 
 
     
     
       27. The apparatus in  claim 25 , wherein determining the first set of address bits includes performing an exclusive-OR (XOR) product operation with an anchor bit among the first set of the scrambling generation bits and with each of the other bits among the first set of the scrambling generation bits, and forming the first set of address bits based on the XOR products. 
     
     
       28. The apparatus of  claim 15 , wherein the complex-valued scrambling sequence is defined by:
     C   long,n ( i )= c   long,1,n ( i )(1+ j (−1) i   c   long,2,n (2 └i/ 2┘))
 
 wherein: 
 i is a chip index starting at 0, 
 the block is a 4-chip symbol block, 
 the binary values of the scrambling sequence are eight binary values based on the binary values c long,1,n (0), c long,2,n  (0), c long,1,n (1), c long,2,n (1), c long,1,n  (2), c long,2,n (2), c long,1,n (3), c long,2,n (3) and correspond to the one set of basic scrambling bits, and 
 c long,1,n (0), c long,2,n  (0), c long,1,n (1), c long,1,n  (2), c long,2,n (2), c long,1,n (3) correspond to the reduced basic scrambling bits.