Video processing apparatus

Abstract

According to one embodiment, a video processing apparatus includes a video data output device which outputs a data packet signal obtained by packetizing a data enable signal and a synchronization packet signal obtained by packetizing a synchronization signal, a transmission device which transmits the data packet signal and the synchronization packet signal, the data packet signal being delayed by a first delay amount and the synchronization packet signal being delayed by a second delay amount, and a timing controller which generates the data enable signal and the synchronization signal so as to set a pulse of the synchronization signal within a blanking period of the data enable signal based on the data packet signal and the synchronization packet signal.

What is claimed is: 
     
       1. A video processing apparatus comprising:
 a video data output device which outputs a data packet signal obtained by packetizing a data enable signal and a synchronization packet signal obtained by packetizing a synchronization signal; 
 a transmission device which transmits the data packet signal and the synchronization packet signal, the data packet signal being delayed by a first delay amount and the synchronization packet signal being delayed by a second delay amount different from the first delay amount; 
 a timing controller which generates the data enable signal and the synchronization signal so as to set a pulse of the synchronization signal within a blanking period of the data enable signal based on the data packet signal and the synchronization packet signal; and 
 a display device which displays a video based on the data enable signal and the synchronization signal generated by the timing controller. 
 
     
     
       2. The apparatus of  claim 1 , wherein the timing controller comprises:
 a counter which starts to count based on the data enable signal; 
 a comparator which compares a count value of an input of the synchronization packet signal obtained by the counter with a count value corresponding to a Min value and a count value corresponding to a Max value in the blanking period; and 
 a timing signal generation circuit which generates the data enable signal and the synchronization signal so as to set a pulse of the synchronization signal within a blanking period of the data enable signal in accordance with a comparison result obtained by the comparator. 
 
     
     
       3. The apparatus of  claim 2 , wherein the timing signal generation circuit sets a pulse of the synchronization signal at a reception timing of the synchronization packet signal when the count value of an input of the synchronization packet signal is not less than the count value corresponding to the Min value and not more than the count value corresponding to the Max value,
 sets a pulse of the synchronization signal at a timing of the count value corresponding to the Min value when the count value of the input of the synchronization packet signal is smaller than the count value corresponding to the Min value, and 
 sets a pulse of the synchronization signal at a timing of the count value corresponding to the Max value when the count value of the input of the synchronization packet signal is larger than the count value corresponding to the Max value. 
 
     
     
       4. The apparatus of  claim 3 , wherein when the count value of the input of the synchronization packet signal is larger than the count value corresponding to the Max value, the synchronization packet signal is discarded. 
     
     
       5. The apparatus of  claim 2 , wherein the counter starts counting with reference to a trailing edge of the data enable signal. 
     
     
       6. The apparatus of  claim 1 , wherein the synchronization signal comprises a horizontal synchronization signal, and the blanking period comprises a horizontal blanking period. 
     
     
       7. The apparatus of  claim 1 , wherein the synchronization signal comprises a vertical synchronization signal, and the blanking period comprises a vertical blanking period. 
     
     
       8. The apparatus of  claim 1 , wherein the timing controller further comprises a first line buffer and a second line buffer configured to alternately store the data packet signals from the video data output device and alternately output the data packet signals. 
     
     
       9. The apparatus of  claim 8 , wherein while the first line buffer outputs a first data packet signal of the data packet signals, the second line buffer stores a second data packet signal of the data packet signals different from the first data packet signal. 
     
     
       10. The apparatus of  claim 1 , wherein the video data output device comprises an application processor. 
     
     
       11. The apparatus of  claim 1 , wherein the transmission device selects and receives a packet signal from any one of a plurality of transmission source devices, selects any one of a plurality of transmission destination devices, and transmits the packet signal. 
     
     
       12. The apparatus of  claim 1 , further comprising a display signal output device configured to convert formats of the data enable signal and the synchronization signal from the timing controller and output the data enable signal and the synchronization signal to the display device.