Formatting audio-video information compliant with first transmission format to second transmission format in integrated circuit for offloading physical layer logic for first transmission format to separate integrated circuit

Abstract

Techniques and mechanisms for formatting digital audio-video (“AV”) information. In an embodiment, interface logic includes circuitry to receive digital AV information which, in one or more respects, is according to or otherwise compatible with a first interface specification. The interface logic changes a format of the digital AV information to allow for subsequent physical layer processing which is according to a second interface specification. In another embodiment, conversion logic receives analog signals according to the second interface specification and, based on such analog signals, performs digital information processing for subsequent generation of other analog signals to be transmitted according to the first interface specification.

What is claimed is:  
     
       1. An apparatus comprising:
 interface circuit logic configured to reformat first digital information based on a correspondence of the first digital information to a first frame format of a first interface specification, wherein the first frame format includes an active portion and a blanking portion, wherein the first interface specification defines a plurality of logical channels for communication based on the first frame format; and 
 first physical layer circuitry coupled to receive the reformatted first digital information from the interface circuit logic, including the first physical layer circuitry to receive sets of bytes each for a different respective cycle of a first clock signal, the sets of bytes comprising a first set of bytes corresponding to the blanking portion, the first set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the first set of bytes which represent data of the plurality of logical channels is less than a total bit capacity of the plurality of logical channels, wherein, based on the reformatted first digital information, the first physical layer circuitry to generate a first analog transmission according to a second interface specification. 
 
     
     
       2. The apparatus of  claim 1 , further comprising link layer logic to generate the first digital information. 
     
     
       3. The apparatus of  claim 2 , wherein the link layer logic to generate the first digital information includes the link layer logic to perform a transition-minimized differential signaling (TMDS) decode operation or a TMDS error reduction coding (TERC) decode operation. 
     
     
       4. The apparatus of  claim 1 , the first set of bytes further comprising bits each for a respective control signal of a plurality of control signals. 
     
     
       5. The apparatus of  claim 4 , wherein the plurality of control signals includes a skip signal to indicate whether the first physical layer circuitry is to skip transmission of data for a transmission period. 
     
     
       6. The apparatus of  claim 1 , the sets of bytes further comprising a second set of bytes corresponding to the blanking portion, the second set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the second set of bytes which represent data of the plurality of logical channels is greater than the total number of bits of the first set of bytes which represent data of the plurality of logical channels. 
     
     
       7. The apparatus of  claim 1 , the sets of bytes further comprising a second set of bytes corresponding to the active portion, the second set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the second set of bytes which represent data of the plurality of logical channels is equal to the total bit capacity of the plurality of logical channels. 
     
     
       8. The apparatus of  claim 1 , further comprising: a second integrated circuit configured to:
 receive the first analog transmission with second physical layer circuitry; 
 generate, based on the received first analog transmission, second digital information including sets of bytes each for a different respective cycle of the first clock signal; 
 reformat the second digital information according to the first frame format; 
 encode the reformatted first digital information to generate third digital information; 
 generate, based on the third digital information, a second analog communication according to the first interface specification. 
 
     
     
       9. A method comprising: with a first integrated circuit:
 reformatting first digital information based on a correspondence of the first digital information to a first frame format of a first interface specification, wherein the first frame format includes an active portion and a blanking portion, wherein the first interface specification defines a plurality of logical channels for communication based on the first frame format; and 
 receiving the reformatted first digital information with first physical layer circuitry, including the first physical layer circuitry receiving sets of bytes each for a different respective cycle of a first clock signal, the sets of bytes comprising a first set of bytes corresponding to the blanking portion, the first set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the first set of bytes which represent data of the plurality of logical channels is less than a total bit capacity of the plurality of logical channels; 
 with the first physical layer circuitry, generating, based on the reformatted first digital information, a first analog transmission according to a second interface specification. 
 
     
     
       10. The method of  claim 9 , further comprising generating the first digital information. 
     
     
       11. The method of  claim 10 , wherein generating the first digital information includes performing a transition-minimized differential signaling (TMDS) decode operation or a TMDS error reduction coding (TERC) decode operation. 
     
     
       12. The method of  claim 9 , the first set of bytes further comprising bits each for a respective control signal of a plurality of control signals. 
     
     
       13. The method of  claim 12 , wherein the plurality of control signals includes a skip signal to indicate whether the first physical layer circuitry is to skip transmission of data for a transmission period. 
     
     
       14. The method of  claim 9 , the sets of bytes further comprising a second set of bytes corresponding to the blanking portion, the second set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the second set of bytes which represent data of the plurality of logical channels is greater than the total number of bits of the first set of bytes which represent data of the plurality of logical channels. 
     
     
       15. The method of  claim 9 , the sets of bytes further comprising a second set of bytes corresponding to the active portion, the second set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the second set of bytes which represent data of the plurality of logical channels is equal to the total bit capacity of the plurality of logical channels. 
     
     
       16. The method of  claim 9 , further comprising: with a second integrated circuit:
 receiving the first analog transmission with second physical layer circuitry; 
 based on the received first analog transmission, generating second digital information including sets of bytes each for a different respective cycle of the first clock signal; 
 reformatting the second digital information according to the first frame format; 
 encoding the reformatted first digital information to generate third digital information; 
 with second physical layer circuitry, generating, based on the third digital information, a second analog communication according to the first interface specification. 
 
     
     
       17. An apparatus comprising:
 first physical layer circuitry to receive a first analog communication according to a first interface specification and to generate, based on the received first analog communication, first digital information including sets of bytes each for a different respective cycle of a first clock signal; 
 conversion circuitry to reformat the first digital information according to a first frame format of a second interface specification, wherein the first frame format includes an active portion and a blanking portion, wherein the first interface specification defines a plurality of logical channels for communication based on the first frame format, wherein the sets of bytes includes a first set of bytes corresponding to the blanking portion, and wherein the conversion circuitry to reformat the first digital information includes:
 for each logical channel of the plurality of logical channels, the conversion circuitry to allocate respective bits of the first set of bytes to the logical channel, wherein a total number of bits of the first set of bytes which are allocated to the plurality of logical channels is less than a total bit capacity of the plurality of logical channels, the conversion circuitry further to encode the reformatted first digital information to generate second digital information; and 
 second physical layer circuitry to generate, based on the second digital information, a second analog communication according to the second interface specification. 
 
 
     
     
       18. The apparatus of  claim 17 , wherein the conversion logic to encode the reformatted first digital information includes the conversion logic to perform a transition-minimized differential signaling (TMDS) encode operation or a TMDS error reduction coding (TERC) encode operation. 
     
     
       19. The apparatus of  claim 17 , wherein the first set of bytes further comprises bits each for a respective control signal of a plurality of control signals. 
     
     
       20. The apparatus of  claim 19 , wherein the plurality of control signals includes a skip signal to indicate whether a transmission period is a skipped transmission period. 
     
     
       21. The apparatus of  claim 17 , the sets of bytes further comprising a second set of bytes corresponding to the blanking portion, the second set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the second set of bytes which represent data of the plurality of logical channels is greater than the total number of bits of the first set of bytes which represent data of the plurality of logical channels. 
     
     
       22. The apparatus of  claim 17 , the sets of bytes further comprising a second set of bytes corresponding to the active portion, the second set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the second set of bytes which represent data of the plurality of logical channels is equal to the total bit capacity of the plurality of logical channels. 
     
     
       23. A method comprising:
 receiving with first physical layer circuitry a first analog communication according to a first interface specification; 
 based on the received first analog communication, generating first digital information including sets of bytes each for a different respective cycle of a first clock signal; 
 reformatting the first digital information according to a first frame format of a second interface specification, wherein the first frame format includes an active portion and a blanking portion, wherein the first interface specification defines a plurality of logical channels for communication based on the first frame format, wherein the sets of bytes includes a first set of bytes corresponding to the blanking portion, and wherein the reformatting includes:
 for each logical channel of the plurality of logical channels, allocating respective bits of the first set of bytes to the logical channel, wherein a total number of bits of the first set of bytes which are allocated to the plurality of logical channels is less than a total bit capacity of the plurality of logical channels; 
 encoding the reformatted first digital information to generate second digital information; and 
 with second physical layer circuitry, generating, based on the second digital information, a second analog communication according to the second interface specification. 
 
 
     
     
       24. The method of  claim 23 , wherein encoding the reformatted first digital information includes performing a transition-minimized differential signaling (TMDS) encode operation or a TMDS error reduction coding (TERC) encode operation. 
     
     
       25. The method of  claim 23 , wherein the first set of bytes further comprises bits each for a respective control signal of a plurality of control signals. 
     
     
       26. The method of  claim 25 , wherein the plurality of control signals includes a skip signal to indicate whether a transmission period is a skipped transmission period. 
     
     
       27. The method of  claim 23 , the sets of bytes further comprising a second set of bytes corresponding to the blanking portion, the second set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the second set of bytes which represent data of the plurality of logical channels is greater than the total number of bits of the first set of bytes which represent data of the plurality of logical channels. 
     
     
       28. The method of  claim 23 , the sets of bytes further comprising a second set of bytes corresponding to the active portion, the second set of bytes including, for each of the plurality of logical channels, respective bits to represent data of the logical channel, wherein a total number of bits of the second set of bytes which represent data of the plurality of logical channels is equal to the total bit capacity of the plurality of logical channels.