Nonvolatile memory device

Abstract

A nonvolatile memory device includes a tunneling region and an erase region formed over a substrate, a selection gate formed over the substrate to overlap with the tunneling region, a floating gate formed over the substrate to be disposed adjacent to the selection gate with a gap therebetween and to overlap with the tunneling region and the erase region, and a charge blocking layer filling the gap.

What is claimed is: 
     
       1. A nonvolatile memory device, comprising:
 a plurality of tunneling regions that are extended in a first direction and arranged to be spaced apart from each other in a second direction intersecting with the first direction; 
 a plurality of erase regions disposed between the tunneling regions, in the second direction; and 
 a plurality of gate lines that are extended in the second direction and arranged to be spaced apart from each other in the first direction, 
 wherein each of the gate lines includes a selection gate going across the tunneling regions, a plurality of floating gates disposed to be adjacent to the selection gate with a gap therebetween and to overlap with the tunneling regions and the erase regions, and a charge blocking layer filling the gap, 
 wherein the selection gate performs a function of a control gate that couples the floating gate, 
 wherein, in each of the gate lines, the floating gates overlap with the tunneling regions that the selection gate goes across, 
 wherein two of the floating gates overlapping with the tunneling regions on both sides of each erase region in the second direction share a corresponding erase region. 
 
     
     
       2. The nonvolatile memory device of  claim 1 , further comprising:
 a plurality of first wells to correspond to the tunneling regions; and 
 a plurality of second wells to correspond to the erase regions and having a conductive type complementary to a conductive type of the first wells. 
 
     
     
       3. The nonvolatile memory device of  claim 2 , wherein the tunneling regions share one first well, and
 the first wells and the second wells are alternately arranged in the second direction. 
 
     
     
       4. The nonvolatile memory device of  claim 2 , wherein the erase regions share one second well and are disposed between the gate lines. 
     
     
       5. The nonvolatile memory device of  claim 1 , wherein among the gate lines, a pair of gate lines disposed adjacent to each other in the first direction has floating gates facing each other or selection gates facing each other. 
     
     
       6. The nonvolatile memory device of  claim 5 , wherein the erase regions are disposed between the pair of gate lines having floating gates facing each other. 
     
     
       7. The nonvolatile memory device of  claim 6 , wherein the floating gates of one gate line of the pair of gate lines and the floating gates of the other gate line of the pair of gate lines face each other and share the erase regions that are disposed between the floating gates of one gate line of the pair of gate lines and the floating gates of the other gate line of the pair of gate lines. 
     
     
       8. The nonvolatile memory device of  claim 1 , wherein each selection gate has a sidewall that faces a sidewall of at least one floating gate. 
     
     
       9. The nonvolatile memory device of  claim 1 , wherein the floating gates are coupled in response to a bias that is applied to the selection gates. 
     
     
       10. The nonvolatile memory device of  claim 1 , wherein the charge blocking layer includes spacers formed on sidewalls of the selection gates and the floating gates. 
     
     
       11. The nonvolatile memory device of  claim 1 , further comprising:
 a first junction region formed in the tunneling regions between a pair of gate lines of which a selection gate of one gate line faces a selection gate of the other gate line, in the first direction; 
 a second junction region formed in the tunneling regions between a pair of gate lines of which floating gates of one gate line faces floating gates of the other gate line in the first direction; 
 a first conductive line extended in the second direction and coupled with the first junction region; 
 a second conductive line extended in the first direction and coupled with the second junction region; and 
 a third conductive line extended in the first direction and coupled with the erase regions. 
 
     
     
       12. The nonvolatile memory device of  claim 11 , wherein the third conductive lines and the second conductive lines are alternately disposed in the second direction. 
     
     
       13. The nonvolatile memory device of  claim 1 , wherein the selection gate and the floating gate are disposed on the same plane.