Pulse generator having a phase and voltage varying pulse width

Abstract

A pulse generator generates a square-wave pulsed signal that has a variable pulse width. The pulse width, which is defined by the delay through a delay line, varies in response to variations in an input voltage, as well as in response to phase differences between a reference clock signal and a trigger signal.

What is claimed is: 
     
       1. A pulse generator comprising:
 a delay line to receive a trigger signal, generate a delayed trigger signal a delay time later in response to the trigger signal, and vary the delay time in response to changes in a magnitude of a phase shift current; 
 a pulse circuit that is connected to the delay line, the pulse circuit to generate a pulsed signal in response to the trigger signal and the delayed trigger signal; 
 an oscillator to generate a reference clock signal; and 
 a phase detector/charge pump that is connected to the delay line, the pulse circuit, and the oscillator, the phase detector/charge pump to generate the phase shift current, detect a difference in phase between an edge of the reference clock signal and an edge of the pulsed signal, and vary the magnitude of the phase shift current in response to the difference in phase. 
 
     
     
       2. The pulse generator of  claim 1  wherein the delay line receives an x-bit control word, and varies the delay time in response to changes in the x-bit control word. 
     
     
       3. The pulse generator of  claim 2  and further comprising a threshold detect/digitizer circuit that is connected to the delay line, the threshold detect/digitizer circuit to change the x-bit word in response to changes in a magnitude of a current magnitude signal. 
     
     
       4. The pulse generator of  claim 3  and further comprising a current sense circuit that is connected to the threshold detect/digitizer circuit, the current sense circuit to sense a magnitude of a timing current and output the current magnitude signal in response, the magnitude of the current magnitude signal represents the magnitude of the timing current. 
     
     
       5. The pulse generator of  claim 4  and further comprising a voltage-to-current converter that is connected to the current sense circuit, the voltage-to-current converter to receive an input voltage, generate the timing current in response to the input voltage, and vary the magnitude of the timing current in response to changes in a magnitude of the input voltage. 
     
     
       6. The pulse generator of  claim 5  and further comprising a regulation circuit that receives an output voltage, and generates the trigger signal in response to changes in the output voltage, the regulation circuit to switch from an integrating averaging feedback mode to a peak-to-peak monitoring mode when a limit signal generated by the phase detector/charge pump indicates that the phase shift current has a maximum magnitude. 
     
     
       7. The pulse generator of  claim 6  wherein:
 the phase detector/charge pump stops detecting a difference in phase between the reference clock signal and the pulsed signal when the phase shift current reaches the maximum magnitude; 
 the phase detector/charge pump stops resumes detecting a difference in phase between the reference clock signal and the pulsed signal in response to a reset signal; and 
 when in the peak-to-peak monitoring mode and the output voltage falls below a regulation voltage, the regulation circuit generates the reset signal and outputs a number of trigger signals until the output voltage exceeds an overshoot voltage. 
 
     
     
       8. The pulse generator of  claim 7  wherein the delay line includes:
 a plurality of delay cells; 
 a plurality of switches that are connected to the plurality of delay cells; and 
 a delay line controller that is connected to the plurality of switches, the delay line controller to close a number of switches in response to the x-bit control word, the x-bit control word to identify a number of delay cells from the plurality of delay cells, the switches to serially connect together the number of delay cells identified by the x-bit word. 
 
     
     
       9. The pulse generator of  claim 8  wherein the pulsed signal has a square waveform with pulse widths that are defined by a difference between the delayed trigger signal and the trigger signal. 
     
     
       10. The pulse generator of  claim 9  wherein the pulse circuit includes:
 a SR flip-flop having a set input that receives the trigger signal, a reset input that receives the delayed trigger signal, and a Q output; and 
 a pulse drive circuit that is connected to the Q output of the SR flip-flop, the pulse drive circuit to drive a signal output from the Q output to form the pulsed signal. 
 
     
     
       11. A method of operating a pulse generator, the method comprising:
 delaying a trigger signal by a delay time to form a delayed trigger signal, and varying the delay time in response to changes in a magnitude of a phase shift current; 
 generating a pulsed signal in response to the trigger signal and the delayed trigger signal; 
 generating a reference clock signal; 
 comparing an edge of the pulsed signal with an edge of the reference clock signal to determine a phase difference; 
 generating the phase shift current; and 
 varying the magnitude of the phase shift current in response to the phase difference. 
 
     
     
       12. The method of  claim 11  and further comprising receiving an x-bit control word, and varying the delay time in response to changes in the x-bit control word. 
     
     
       13. The method of  claim 12  and further comprising changing the x-bit word in response to changes in a magnitude of a current magnitude signal. 
     
     
       14. The method of  claim 13  and further comprising sensing a magnitude of a timing current, and outputting the current magnitude signal in response, the magnitude of the current magnitude signal representing the magnitude of the timing current. 
     
     
       15. The method of  claim 14  and further comprising receiving an input voltage, generating the timing current in response to the input voltage, and varying the magnitude of the timing current in response to changes in a magnitude of the input voltage. 
     
     
       16. The method of  claim 15  and further comprising generating the trigger signal in response to changes in an output voltage, and switching from an integrating averaging feedback mode to a peak-to-peak monitoring mode when a limit signal generated by the phase detector/charge pump indicates that the phase shift current has a maximum magnitude. 
     
     
       17. The method of  claim 16  and further comprising:
 stopping a detection of a difference in phase between the reference clock signal and the pulsed signal when the phase shift current reaches the maximum magnitude; 
 resuming the detection of the difference in phase between the reference clock signal and the pulsed signal in response to a reset signal; and 
 when in the peak-to-peak monitoring mode and the output voltage falls below a regulation voltage, generating the reset signal and outputs a number of trigger signals until the output voltage exceeds an overshoot voltage. 
 
     
     
       18. The method of  claim 17  wherein the trigger signal is delayed by a number of serially-connected delay cells to form the delayed trigger signal, the delay time changing in response to changes in the number of serially-connected delay cells, the x-bit control word identifying a number of delay cells to be serially connected together. 
     
     
       19. The method of  claim 18  wherein the pulsed signal has a square waveform with pulse widths that are defined by a difference between the delayed trigger signal and the trigger signal. 
     
     
       20. The method of  claim 19  wherein generating the pulsed signal includes:
 setting a SR flip-flop in response to the trigger signal, resetting the SR flip-flop in response to the delayed trigger signal, and outputting a Q output signal that has a logic state determined by a logic state of the trigger signal and a logic state of the delay trigger signal; and 
 driving the Q output signal to form the pulsed signal.