Voltage level shifter with a low-latency voltage boost circuit

Abstract

Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level shifting circuits provide significantly lower latency compared to conventional level shifters (e.g., latency reduced by at least a factor of two). Offering consistent latency over the simulation corners, level shifting circuits described herein also provide significantly lower power consumption and reduced duty cycle distortion compared to conventional level shifters.

What is claimed is: 
     
       1. A circuit for level shifting an input signal from a first voltage level to a second voltage level, comprising:
 an alternating current (AC)-coupled voltage boost circuit configured to boost the input signal such that first and second nodes of the voltage boost circuit have a voltage value greater than or equal to the first voltage level; 
 a first logic inverter configured to produce a first output signal having a magnitude up to the second voltage level, wherein the first node of the voltage boost circuit is directly connected to an input of the first logic inverter and to a first capacitor configured to receive a logical inverse of the input signal; and 
 a second logic inverter configured to produce a second output signal having a magnitude up to the second voltage level, wherein the second node of the voltage boost circuit is directly connected to an input of the second logic inverter and to a second capacitor configured to receive the input signal, wherein the voltage boost circuit is powered by a third voltage level that is lower than the second voltage level, and wherein the first voltage level is equal to the third voltage level. 
 
     
     
       2. The level shifting circuit of  claim 1 , wherein the voltage boost circuit comprises first and second switches configured, when closed, to connect the third voltage level to the first and second nodes of the voltage boost circuit, respectively, wherein the second node of the voltage boost circuit is a control for the first switch, and wherein the first node of the voltage boost circuit is a control for the second switch. 
     
     
       3. The level shifting circuit of  claim 2 , wherein the first and second switches comprise first and second n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), wherein a gate of the first transistor is coupled to the second node of the voltage boost circuit, wherein a source of the first transistor is coupled to the first node of the voltage boost circuit, wherein a drain of the first transistor is coupled to the third voltage level, wherein a gate of the second transistor is coupled to the first node of the voltage boost circuit, wherein a source of the second transistor is coupled to the second node of the voltage boost circuit, and wherein a drain of the second transistor is coupled to the third voltage level. 
     
     
       4. The level shifting circuit of  claim 1 , wherein the voltage value of the first and second nodes is between the first voltage level and a sum of the first and third voltage levels, inclusive. 
     
     
       5. The level shifting circuit of  claim 1 , wherein the third voltage level is powered by and is configured to track the second voltage level via a tracking circuit. 
     
     
       6. The level shifting circuit of  claim 5 , wherein the tracking circuit comprises a p-channel metal-oxide-semiconductor field-effect transistor (MOSFET), wherein a source of the MOSFET is coupled to the second voltage level, wherein a drain of the MOSFET is coupled to a gate of the MOSFET, and wherein the gate of the MOSFET is coupled to the third voltage level. 
     
     
       7. The level shifting circuit of  claim 1 , wherein the first or second node of the voltage boost circuit is configured to be initialized to a starting value before the input signal becomes dynamic. 
     
     
       8. The level shifting circuit of  claim 1 , wherein the logical inverse of the input signal drives another input of the first logic inverter and wherein the input signal drives another input of the second logic inverter. 
     
     
       9. The level shifting circuit of  claim 8 , wherein the logical inverse of the input signal is directly connected to the other input of the first logic inverter and wherein the input signal is directly connected to the other input of the second logic inverter. 
     
     
       10. The level shifting circuit of  claim 1 , wherein at least one of the first or second logic inverter comprises a complementary metal-oxide-semiconductor (CMOS) inverter. 
     
     
       11. The level shifting circuit of  claim 1 , wherein the second voltage level is higher than the first voltage level. 
     
     
       12. The level shifting circuit of  claim 1 , wherein the second output signal is a logical inverse of the first output signal. 
     
     
       13. An electronic signal converter comprising:
 a circuit for level shifting an input signal from a first voltage level to a second voltage level, the circuit comprising:
 an alternating current (AC)-coupled voltage boost circuit powered by the first voltage level and configured to boost the input signal such that first and second nodes of the voltage boost circuit have a voltage value greater than or equal to the first voltage level; 
 a first logic inverter configured to produce a first output signal having a magnitude up to the second voltage level, wherein the first node of the voltage boost circuit is directly connected to an input of the first logic inverter and to a first capacitor configured to receive a logical inverse of the input signal; and 
 a second logic inverter configured to produce a second output signal having a magnitude up to the second voltage level, wherein the second node of the voltage boost circuit is directly connected to an input of the second logic inverter and to a second capacitor configured to receive the input signal, wherein the voltage boost circuit is powered by a third voltage level that is lower than the second voltage level, and wherein the first voltage level is equal to the third voltage level. 
 
 
     
     
       14. The converter of  claim 13 , wherein the input signal comprises a sampling clock signal for the converter. 
     
     
       15. A method of level shifting an input signal from a first voltage level to a second voltage level, comprising:
 boosting the input signal in an alternating current (AC)-coupled voltage boost circuit, such that first and second nodes of the voltage boost circuit have a voltage value greater than or equal to the first voltage level; 
 outputting, from a first logic inverter, a first output signal having a magnitude up to the second voltage level, wherein the first node of the voltage boost circuit is directly connected to an input of the first logic inverter and to a first capacitor configured to receive a logical inverse of the input signal; and 
 outputting, from a second logic inverter, a second output signal having a magnitude up to the second voltage level, wherein the second node of the voltage boost circuit is directly connected to an input of the second logic inverter and to a second capacitor configured to receive the input signal, wherein the voltage boost circuit is powered by a third voltage level that is lower than the second voltage level, and wherein the first voltage level is equal to the third voltage level.