Power gate for latch-up prevention

Abstract

In an embodiment of the invention, power is provided to an SRAM array without causing latch-up by charging the positive voltage node in the SRAM array and the Nwell regions in the SRAM at approximately the same rate.

What is claimed is: 
     
       1. A circuit for providing power to a static random access memory (SRAM) array without causing latch-up comprising:
 a first PFET, the first PFET having a source, a drain and a gate wherein the drain of the first PFET is connected to a positive voltage node in the SRAM array, the source of the first PFET is connected to a first power supply and the gate of the first PFET is connected to a first control signal; 
 a second PFET, the second PFET having a source, a drain and a gate wherein the drain of the second PFET is connected to at least one Nwell in the SRAM array, the source of the second PFET is connected to a second power supply and the gate of the second PFET is connected to the first control signal; and 
 a third PFET, the third PFET having a source, a drain and a gate wherein the drain of the third PFET is connected to the least one Nwell in the SRAM array, the source of the third PFET is connected to the positive voltage node in the SRAM array and the gate of the third PFET is connected to a second control signal. 
 
     
     
       2. The circuit of  claim 1  wherein the second control signal is driven to a logical low level before the first control signal is driven to a logical low level. 
     
     
       3. The circuit of  claim 1  wherein the first and second control signals are driven to a logical low level at approximately the same time. 
     
     
       4. A circuit for providing power to a static random access memory (SRAM) array without causing latch-up comprising:
 a first PFET, the first PFET having a source, a drain and a gate wherein the drain of the first PFET is connected to a positive voltage node in the SRAM array, the source of the first PFET is connected to a first power supply and the gate of the first PFET is connected to a first control signal; 
 a second PFET, the second PFET having a source, a drain and a gate wherein the drain of the second PFET is connected to all Nwells in the SRAM array, the source of the second PFET is connected to a second power supply and the gate of the second PFET is connected to the first control signal; and 
 a third PFET, the third PFET having a source, a drain and a gate wherein the drain of the third PFET is connected to all Nwells in the SRAM array, the source of the third PFET is connected to the positive voltage node in the SRAM array and the gate of the third PFET is connected to a second control signal. 
 
     
     
       5. The circuit of  claim 1  wherein the second control signal is driven to a logical low level before the first control signal is driven to a logical low level. 
     
     
       6. The circuit of  claim 1  wherein the first and second control signals are driven to a logical low level at approximately the same time.