Low leakage flip-flop circuit

Abstract

An integrated circuit having reduced power consumption includes a clock-gating cell, a transistor and a flip-flop. The clock-gating cell receives a dynamic enable signal, generates a latched-enable signal and gates a clock signal provided to the flip-flop. The flip-flop includes first and second latches. The transistor receives an inverted latched-enable signal from the clock-gating cell and switches ON or OFF based on the logic state of the inverted latched-enable signal. The transistor provides a voltage signal to the flip-flop circuit based on the state of the flip-flop in order to control the state of the flip-flop, which reduces power consumption of the integrated circuit.

The invention claimed is: 
     
       1. An integrated circuit, comprising:
 a clock-gating cell for receiving an enable signal and a clock signal and generating a gated-clock signal and a latched-enable signal; 
 a transistor having a gate terminal connected to the clock-gating cell by way of a first NOT gate for receiving an inverted latched-enable signal, a first diffusion terminal for receiving a supply voltage signal, and a second diffusion terminal for providing the supply voltage signal when the inverted latched-enable signal is in a first logic state; 
 a first latch having an input terminal for receiving an input signal, a first power terminal connected to the second diffusion terminal of the transistor for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the clock-gating cell for receiving the gated-clock signal, and an output terminal for outputting an intermediate output signal; and 
 a second latch having an input terminal connected to the output terminal of the first latch for receiving the intermediate output signal, a first power terminal for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the clock-gating cell by way of a second NOT gate for receiving an inverted gated-clock signal, and an output terminal for outputting an output signal. 
 
     
     
       2. The integrated circuit of  claim 1 , wherein the clock-gating cell comprises:
 a third latch having an input terminal for receiving the enable signal, a first power terminal for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal for receiving the clock signal, and an output terminal for outputting the latched-enable signal; and 
 an AND gate having a first input terminal connected to the output terminal of the third latch for receiving the latched-enable signal, a second input terminal for receiving the clock signal, and an output terminal for generating the gated-clock signal. 
 
     
     
       3. The integrated circuit of  claim 2 , wherein the first and third latches each comprise a negative level-sensitive latch and the second latch comprises a positive level-sensitive latch. 
     
     
       4. The integrated circuit of  claim 2 , wherein the first and third latches each comprise a positive level-sensitive latch and the second latch comprises a negative level-sensitive latch. 
     
     
       5. The integrated circuit of  claim 2 , wherein the first, second and third latches each comprise a D-type latch. 
     
     
       6. The integrated circuit of  claim 1 , wherein the transistor is switched off when the inverted latched-enable signal is in a second logic state, thereby switching off the first latch. 
     
     
       7. The integrated circuit of  claim 6 , wherein the first logic state is a logic low state and the second logic state is a logic high state. 
     
     
       8. The integrated circuit of  claim 1 , wherein the transistor comprises a p-channel metal-oxide semiconductor (PMOS) transistor. 
     
     
       9. An integrated circuit, comprising:
 a clock-gating cell for receiving an enable signal and a clock signal and generating a gated-clock signal and a latched-enable signal; 
 a first latch having an input terminal for receiving an input signal, a first power terminal for receiving a supply voltage signal, a clock terminal connected to the clock-gating cell for receiving the gated-clock signal, and an output terminal for outputting an intermediate output signal; 
 a second latch having an input terminal connected to the output terminal of the first latch for receiving the intermediate output signal, a first power terminal for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the clock-gating cell by way of a first NOT gate for receiving an inverted gated-clock signal, and an output terminal for outputting an output signal; and 
 a transistor having a gate terminal connected to the clock-gating cell for receiving a latched-enable signal, a first diffusion terminal connected to a second power terminal of the first latch, and a second diffusion terminal connected to ground, wherein the transistor is switched on when the latched-enable signal is in a first logic state. 
 
     
     
       10. The integrated circuit of  claim 9 , wherein the clock-gating cell comprises:
 a third latch having an input terminal for receiving the enable signal, a first power terminal for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal for receiving the clock signal, and an output terminal for outputting the latched-enable signal; and 
 an AND gate having a first input terminal connected to the output terminal of the third latch for receiving the latched-enable signal, a second input terminal for receiving the clock signal, and an output terminal for generating the gated-clock signal. 
 
     
     
       11. The integrated circuit of  claim 10 , wherein the first and third latches each comprise a negative level-sensitive latch and the second latch comprises a positive level-sensitive latch. 
     
     
       12. The integrated circuit of  claim 10 , wherein the first, second and third latches each comprise a D-type latch. 
     
     
       13. The integrated circuit of  claim 9 , wherein the transistor is switched off when the latched-enable signal is in a second logic state thereby switching off the first latch. 
     
     
       14. The integrated circuit of  claim 13 , wherein the first logic state is a logic high state and the second logic state is a logic low state. 
     
     
       15. The integrated circuit of  claim 9 , wherein the transistor is an n-channel metal-oxide semiconductor (NMOS) transistor. 
     
     
       16. An integrated circuit, comprising:
 a first latch having an input terminal for receiving an enable signal, a first power terminal for receiving a supply voltage signal, a second power terminal connected to ground, a clock terminal for receiving a clock signal, and an output terminal for generating a latched-enable signal; 
 an AND gate having a first input terminal connected to the output terminal of the first latch for receiving the latched-enable signal, a second input terminal for receiving the clock signal, and an output terminal for generating a gated-clock signal; 
 a p-channel metal oxide semiconductor (PMOS) transistor having a gate terminal connected to the output terminal of the first latch by way of a first NOT gate for receiving an inverted latched-enable signal, a first diffusion terminal for receiving the supply voltage signal, and a second diffusion terminal for providing the supply voltage signal when the inverted latched-enable is in a first logic state; 
 a second latch having an input terminal for receiving an input signal, a first power terminal connected to the second diffusion terminal of the PMOS transistor for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the output terminal of the AND gate for receiving the gated-clock signal, and an output terminal for outputting an intermediate output signal; and 
 a third latch having an input terminal connected to the output terminal of the second latch for receiving the intermediate output signal, a first power terminal for receiving the supply voltage signal, a second power terminal connected to ground, a clock terminal connected to the output terminal of the AND gate by way of a second NOT gate for receiving an inverted gated-clock signal, and an output terminal for outputting an output signal. 
 
     
     
       17. The integrated circuit of  claim 16 , wherein the first and second latches each comprise a negative level-sensitive latch and the third latch comprises a positive level-sensitive latch. 
     
     
       18. The integrated circuit of  claim 16 , wherein the first, second and third latches each comprise a D-type latch. 
     
     
       19. The integrated circuit of  claim 16 , wherein the PMOS transistor is switched off when the inverted latched-enable signal is in a second logic state, thereby switching off the second latch. 
     
     
       20. The integrated circuit of  claim 19 , wherein the first logic state is a logic low state and the second logic state is a logic high state.