Adjustable PWM method to increase low speed starting torque and inverter voltage measurement accuracy

Abstract

Methods, control apparatus and computer readable mediums are presented for controlling a switching inverter in which a controller selectively suspends PWM carrier signals to provide inverter switching control signals using zero vectors in response to a maximal pulse width value for a present PWM half cycle being greater than a threshold value, and accumulates a present output control value for individual output phases for use in a subsequent PWM half cycle for selective effective reduction in switching frequency for low-speed operation while maintaining high frequency control loop sampling.

The following is claimed: 
     
       1. A method for controlling a switching inverter, the method comprising:
 determining a duty ratio for each output phase of the switching inverter for a present pulse width modulation (PWM) half cycle; 
 determining, for each output phase, a present output control value for the present PWM half cycle as a sum of a previous output control value corresponding to a previous PWM half cycle and the duty ratio corresponding to the present PWM half cycle; 
 determining a pulse width value for the present PWM half cycle according to a maximal one of the present output control values or a maximal present output control value difference between two phases for the present PWM half cycle; 
 selectively generating switching control signals to operate the switching inverter for the present PWM half cycle according to the present output control values in response to the pulse width value for the present PWM half cycle being greater than a threshold value; 
 selectively resetting the present output control values to zero in response to the pulse width value for the present PWM half cycle being greater than the threshold value; and 
 selectively generating the switching control signals to operate the switching inverter for the present PWM half cycle according to a zero vector in response to the pulse width value for the present PWM half cycle being less than or equal to the threshold value. 
 
     
     
       2. The method of  claim 1 , wherein determining the pulse width value for the present PWM half cycle comprises;
 determining the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle; and 
 multiplying the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle by a PWM cycle value corresponding to a full PWM cycle. 
 
     
     
       3. The method of  claim 1 , comprising:
 selectively suspending ramping of carriers for each output phase for the present PWM half cycle in response to the pulse width value for the present PWM half cycle being less than or equal to the threshold value. 
 
     
     
       4. The method of  claim 3 , comprising:
 selectively resuming the ramping of the carriers for each output phase for the present PWM half cycle for generating the switching control signals in response to the pulse width value for the present PWM half cycle being greater than a threshold value. 
 
     
     
       5. The method of  claim 1 , wherein the threshold value is greater than a rise time variation of switches of the switching inverter. 
     
     
       6. The method of  claim 1 , wherein the duty ratio for each output phase is determined for the present PWM half cycle according to a voltage-frequency control loop. 
     
     
       7. The method of  claim 1 , wherein the duty ratio for each output phase is determined for the present PWM half cycle at a peak or valley of carriers for each output phase for the present PWM half cycle. 
     
     
       8. The method of  claim 7 , comprising:
 selectively suspending ramping of the carriers for each output phase for the present PWM half cycle in response to the pulse width value for the present PWM half cycle being less than or equal to the threshold value; and 
 selectively resuming the ramping of the carriers for each output phase for the present PWM half cycle for generating the switching control signals in response to the pulse width value for the present PWM half cycle being greater than a threshold value. 
 
     
     
       9. A non-transitory computer readable medium with computer executable instructions for controlling a switching inverter, the computer readable medium comprising computer executable instructions for:
 determining a duty ratio for each output phase of the switching inverter for a present pulse width modulation (PWM) half cycle; 
 determining, for each output phase, a present output control value for the present PWM half cycle as a sum of a previous output control value corresponding to a previous PWM half cycle and the duty ratio corresponding to the present PWM half cycle; 
 determining a pulse width value for the present PWM half cycle according to a maximal one of the present output control values or a maximal present output control value difference between two phases for the present PWM half cycle; 
 selectively generating switching control signals to operate the switching inverter for the present PWM half cycle according to the present output control values in response to the pulse width value for the present PWM half cycle being greater than a threshold value; 
 selectively resetting the present output control values to zero in response to the pulse width value for the present PWM half cycle being greater than the threshold value; and 
 
       selectively generating the switching control signals to operate the switching inverter for the present PWM half cycle according to a zero vector in response to the pulse width value for the present PWM half cycle being less than or equal to the threshold value. 
     
     
       10. An apparatus for controlling a multiphase inverter, comprising:
 an electronic memory; and 
 at least one processor programmed to: 
 determine a duty ratio for each output phase of the multiphase inverter for a pulse width modulation (PWM) half cycle; 
 determine, for each output phase, a present output control value for the present PWM half cycle as a sum of a previous output control value corresponding to a previous PWM half cycle and the duty ratio corresponding to the present PWM half cycle; 
 determine a pulse width value for the present PWM half cycle according to a maximal one of the present output control values or a maximal present output control value difference between two phases for the present PWM half cycle; 
 selectively generate switching control signals to operate the switching inverter for the present PWM half cycle according to the present output control values in response to the pulse width value for the present PWM half cycle being greater than a threshold value; 
 selectively reset the present output control values to zero in response to the pulse width value for the present PWM half cycle being greater than the threshold value; and 
 selectively generate the switching control signals to operate the switching inverter for the present PWM half cycle according to a zero vector in response to the pulse width value for the present PWM half cycle being less than or equal to the threshold value. 
 
     
     
       11. The apparatus of  claim 10 , wherein the at least one processor is programmed to implement a voltage-frequency control loop relating a setpoint inverter output frequency to phase output voltages of the switching inverter to determine the duty ratio for each output phase of the switching inverter for the present PWM half cycle. 
     
     
       12. The apparatus of  claim 10 , wherein the at least one processor is programmed to determine the duty ratio for each output phase for the present PWM half cycle at a peak or valley of carriers for each output phase for the present PWM half cycle. 
     
     
       13. The apparatus of  claim 12 , wherein the at least one processor is programmed to:
 selectively suspend ramping of the carriers for each output phase for the present PWM half cycle in response to the pulse width value for the present PWM half cycle being less than or equal to the threshold value; and 
 selectively resume the ramping of the carriers for each output phase for the present PWM half cycle to generate the switching control signals in response to the pulse width value for the present PWM half cycle being greater than a threshold value. 
 
     
     
       14. The apparatus of  claim 13 , wherein the threshold value is greater than a rise time variation of switches of the switching inverter. 
     
     
       15. The apparatus of  claim 14 , wherein the at least one processor is programmed to determine the pulse width value for the present PWM half cycle by;
 determining the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle; and 
 multiplying the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle by a PWM cycle value corresponding to a full PWM cycle. 
 
     
     
       16. The apparatus of  claim 13 , wherein the at least one processor is programmed to determine the pulse width value for the present PWM half cycle by;
 determining the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle; and 
 multiplying the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle by a PWM cycle value corresponding to a full PWM cycle. 
 
     
     
       17. The apparatus of  claim 12 , wherein the at least one processor is programmed to determine the pulse width value for the present PWM half cycle by;
 determining the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle; and 
 multiplying the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle by a PWM cycle value corresponding to a full PWM cycle. 
 
     
     
       18. The apparatus of  claim 10 , wherein the threshold value is greater than a rise time variation of switches of the switching inverter. 
     
     
       19. The apparatus of  claim 18 , wherein the at least one processor is programmed to determine the pulse width value for the present PWM half cycle by;
 determining the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle; and 
 multiplying the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle by a PWM cycle value corresponding to a full PWM cycle. 
 
     
     
       20. The apparatus of  claim 10 , wherein the at least one processor is programmed to determine the pulse width value for the present PWM half cycle by;
 determining the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle; and 
 multiplying the maximal one of the present output control values or the maximal present output control value difference between two phases for the present PWM half cycle by a PWM cycle value corresponding to a full PWM cycle.