Method and layout of an integrated circuit

Abstract

An integrated circuit layout includes a P-type active region and an N-type active region, and a plurality of trunks. The integrated circuit layout further includes a first metal connection connected to the P-type active region; and a second metal connection connected to the N-type active region. Each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection. Each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection. A first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks.

What is claimed is: 
     
       1. An integrated circuit layout, comprising:
 a P-type active region and an N-type active region; 
 a plurality of trunks; 
 a first metal connection connected to the P-type active region; and 
 a second metal connection connected to the N-type active region, 
 wherein
 each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection; 
 each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection; and 
 a first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks. 
 
 
     
     
       2. The integrated circuit layout of  claim 1 , wherein the first metal connection includes a plurality of jogs, and the plurality of jogs extends from a side of the first metal connection opposite the plurality of trunks. 
     
     
       3. The integrated circuit layout of  claim 2 , further comprising a power supply line extending parallel to the first metal connection, wherein the power supply line comprises a plurality of protrusions extending from a surface of the power supply line closest to the first metal connection. 
     
     
       4. The integrated circuit layout of  claim 3 , wherein the plurality of protrusions is arranged in an alternating fashion with the plurality of jogs in a direction parallel to the power supply line. 
     
     
       5. The integrated circuit layout of  claim 1 , further comprising an output line connected to the first metal connection and to the second metal connection. 
     
     
       6. The integrated circuit layout of  claim 5 , wherein the output line is located on a level above the plurality of trunks, the output line is connected to the first metal connection by at least one first via, and the output line is connected to the second metal connection by at least one second via. 
     
     
       7. The integrated circuit layout of  claim 6 , wherein a width of the output line is equal to a width of the width of the first trunk of the plurality of trunks. 
     
     
       8. The integrated circuit layout of  claim 1 , further comprising a metal structure connected to the P-type active region and to the N-type active region, wherein the metal structure is separated from the plurality of trunks, the first metal connection and the second metal connection. 
     
     
       9. A cell layout, comprising:
 a P-type active region and an N-type active region; 
 a plurality of trunks; 
 a first metal connection connected to the P-type active region; 
 a second metal connection connected to the N-type active region; 
 a VDD power supply line connected to the P-type active region; and 
 a VSS power supply line connected to the N-type active region, 
 wherein
 each trunk of the plurality of trunks is electrically connected with the first metal connection and the second metal connection; 
 each trunk of the plurality of trunks is substantially perpendicular to the first metal connection and the second metal connection; 
 each trunk of the plurality of trunks is substantially perpendicular to the VDD power supply line and the VSS power supply line; and 
 a first trunk of the plurality of trunks has a width wider than a width of other trunks of the plurality of trunks and is arranged to be located between two groups of trunks. 
 
 
     
     
       10. The cell layout of  claim 9 , wherein the second metal connection includes a plurality of jogs, and the plurality of jogs extends from a side of the second metal connection opposite the plurality of trunks. 
     
     
       11. The cell layout of  claim 10 , wherein the VSS power supply line comprises a plurality of protrusions extending toward the second metal connection. 
     
     
       12. The cell layout of  claim 11 , wherein the plurality of protrusions is arranged in an alternating fashion with the plurality of jogs in a direction parallel to the VSS power supply line. 
     
     
       13. The cell layout of  claim 9 , further comprising an output line connected to the first metal connection through at least one via and to the second metal connection through at least one via. 
     
     
       14. The cell layout of  claim 13 , wherein a width of the output line is equal to a width of the width of the first trunk of the plurality of trunks. 
     
     
       15. A method of forming an integrated circuit layout, the method comprising:
 forming a plurality of trunks, each trunk of the plurality of trunks coupled with and perpendicular to a first metal line and a second metal line, the first metal line being coupled with a plurality of PMOS transistors, the second metal line being coupled with a plurality of NMOS transistors, wherein a width of the first trunk is substantially larger than widths of other trunks of the plurality of trunks; 
 forming a VDD power supply line coupled with the plurality of PMOS transistors; 
 forming a VSS power supply line coupled with the plurality of NMOS transistors; 
 generating, using a processor, pre-coloring information for each of the first metal line, the second metal line, the VDD power supply line, and the VSS power supply line; and 
 assigning, using the processor, each of the first metal line, the second metal line, the VDD power supply line, and the VSS power supply line to a mask based on the pre-coloring information. 
 
     
     
       16. The method of  claim 15 , wherein the assigning comprises assigning the first metal line and the second metal line to a first mask. 
     
     
       17. The method of  claim 16 , wherein the assigning comprises assigning at least one of the VDD power supply line or the VSS power supply line to a second mask different from the first mask. 
     
     
       18. The method of  claim 15 , further comprising forming a metal structure on a same metal level as the first metal line, the second metal line, the VDD power supply line, and the VSS power supply line. 
     
     
       19. The method of  claim 18 , further comprising assigning the metal structure to a same mask as at least one of the first metal line or the second metal line. 
     
     
       20. The method of  claim 18 , further comprising assigning the metal structure to a same mask as at least one of the VDD power supply line or the VSS power supply line.