Non-volatile semiconductor storage device, and memory system

Abstract

A non-volatile semiconductor storage device includes an memory cell array including first and second blocks, each of which includes a plurality of memory strings each having n (n: natural number) memory cells, and a optionally a peripheral circuit for controlling the memory cell array. In this non-volatile semiconductor storage device, n signal lines are arranged in the first block, and m (n>m, m: natural number) signal lines are arranged in the second block, such that the second block size is smaller than the first block size.

What is claimed is: 
     
       1. A non-volatile semiconductor storage device comprising:
 a memory cell array which includes a plurality of memory cells divided into first and second blocks, each of which includes a plurality of memory strings each having n (n: natural number) memory cells, the first memory block including a first memory string of n memory cells electrically connected in series and the second memory block including a second memory string of n memory cells electrically connected in series, wherein 
 n first signal lines extending in a first direction are arranged in the first block along a second direction different from the first direction, the first signal lines being electrically connected to first word lines, each of the first word lines being electrically connected to a gate of a respective one of the memory cells of the first memory string and not electrically connected to a gate of any other memory cell of the first memory string, each of the first signal lines being electrically connected to a respective one of the first word lines and not electrically connected to any of the other first word lines, and 
 m (n>m, m: natural number) second signal lines extending in the first direction are arranged in the second block along the second direction, the second signal lines being electrically connected to second word lines, each of the second word lines being electrically connected to a gate of a respective one of the memory cells of the second memory string and not electrically connected to a gate of any other memory cell of the second memory string, at least one of the second signal lines being electrically connected to more than one of the second word lines. 
 
     
     
       2. The non-volatile semiconductor storage device according to  claim 1 , wherein a width of the first block in the second direction is greater than that of the second block in the second direction. 
     
     
       3. The non-volatile semiconductor storage device according to  claim 2 , wherein
 the first word lines and the second word lines are respectively stacked above a substrate, and 
 the second word lines include a first group, a second group, and a third group between the first group and the second group, each of the second word lines in the first and second groups being commonly electrically connected to one of the second signal lines with at least one of the other second word lines in the first and second groups. 
 
     
     
       4. The non-volatile semiconductor storage device according to  claim 3 , wherein
 the first signal lines are electrically connected to the first word lines through n first plugs, and 
 the second signal lines are electrically connected to the second word lines through n second plugs, at least one of the second signal lines being commonly electrically connected to k second word lines through k second plugs, where k is two or more. 
 
     
     
       5. The non-volatile semiconductor storage device according to  claim 4 , wherein
 the second word lines in the first group are commonly electrically connected to one of the second signal lines through multiple second plugs, and 
 the second word lines in the second group are commonly electrically connected to another one of the second signal lines through multiple second plugs. 
 
     
     
       6. The non-volatile semiconductor storage device according to  claim 5 , wherein
 the second word lines in the third group are each independently electrically connected to one of the second signal lines through one of the second plugs. 
 
     
     
       7. The non-volatile semiconductor storage device according to  claim 6 , wherein the number of second word lines in the third group is three. 
     
     
       8. The non-volatile semiconductor storage device according to  claim 7 , further comprising:
 a peripheral circuit including a voltage generating circuit configured to generate a reading voltage, a first voltage which brings the memory cell into an ON state, and a second voltage which brings the memory cell into an ON state, and wherein 
 the voltage generating circuit, when reading out data from a memory cell in the second block, supplies the reading voltage to a gate of the memory cell through a second word line in the third group and the first voltage to the second word lines connected to gates of the memory cells adjacent to the memory cell, and the second voltage to the remaining second word lines. 
 
     
     
       9. The non-volatile semiconductor storage device according to  claim 2 , wherein
 the second block stores management data indicating addresses of other blocks having a width in the first direction that is less than that of the first block. 
 
     
     
       10. A memory system comprising:
 a non-volatile semiconductor storage device including
 a memory cell array which includes a plurality of memory cells divided into first and second blocks, each of which includes a plurality of memory strings each having n (n: natural number) memory cells, the first memory block including a first memory string of memory cells electrically connected in series and the second memory block including a second memory string of memory cells electrically connected in series, wherein 
 n first signal lines extending in a first direction are arranged in the first block along a second direction different from the first direction, the first signal lines being electrically connected to first word lines, each of the first word lines being electrically connected to a gate of a respective one of the memory cells of the first memory string and not electrically connected to a gate of any other memory cell of the first memory string, each of the first signal lines being electrically connected to a respective one of the first word lines and not electrically connected to any of the other first word lines, and 
 m (n>m, m: natural number) second signal lines extending in the first direction are arranged in the second block along the second direction, the second signal lines being electrically connected to a gate of a respective one of the memory cells of the second memory string and not electrically connected to a gate of any other memory cell of the second memory string, at least one of the second signal lines being electrically connected to more than one of the second word lines; and 
 
 a memory controller configured to control the non-volatile semiconductor storage device, wherein 
 the memory controller, when the non-volatile semiconductor storage device is activated, executes a first reading operation on memory cells in the second block to determine if a third block, which is targeted in a second reading operation, has a block size smaller than that of the first block. 
 
     
     
       11. The memory system according to  claim 10 , wherein the second block stores management data. 
     
     
       12. The memory system according to  claim 10 , wherein a width of the first block in the second direction is greater than that of the second block in the second direction. 
     
     
       13. The memory system according to  claim 10 , wherein
 the first word lines and the second word lines are respectively stacked on a substrate, and 
 the second word lines include a first group, a second group, and a third group between the first group and the second group, each of the second word lines in the first and second groups being commonly electrically connected to one of the second signal lines with at least one of the other second word lines in the first and second groups. 
 
     
     
       14. The memory system according to  claim 13 , wherein
 the first signal lines are electrically connected to the first word lines through n first plugs, and 
 the second signal lines are electrically connected to the second word lines through n second plugs, at least one of the second signal lines being commonly electrically connected to k second word lines through k second plugs, where k is two or more. 
 
     
     
       15. The memory system according to  claim 14 , wherein
 the second word lines in the first group are commonly electrically connected to one of the second signal lines through multiple second plugs, and 
 the second word lines in the second group are commonly electrically connected to another one of the second signal lines through multiple second plugs. 
 
     
     
       16. The memory system according to  claim 15 , wherein
 the second word lines in the third group are each independently electrically connected to one of the second signal lines through one of the second plugs. 
 
     
     
       17. The memory system according to  claim 16 , wherein the number of second word lines in the third group is three. 
     
     
       18. The memory system according to  claim 13 , further comprising:
 a peripheral circuit including a voltage generating circuit configured to generate a reading voltage, a first voltage which brings the memory cell into an ON state, and a second voltage which brings the memory cell into an ON state, and wherein 
 the voltage generating circuit, when reading out data from a memory cell in the second block, supplies the reading voltage to a gate of the memory cell through a second word line in the third group and the first voltage to the second word lines connected to gates of the memory cells adjacent to the memory cell, and the second voltage to the remaining second word lines.