Indicating critical battery status in mobile devices

Abstract

An integrated circuit such as a SoC may indicate the critical battery status without powering-on a substantial portion including the host processing cores. The SoC may include a microcontroller, which may cause the critical battery status data to be stored in a static memory and the display unit may retrieve such data from the static memory to display a visual symbol on the screen. The other portions of the SoC such as the dynamic memory, system agent, media processors, and memory controller hubs may be powered-down while the critical battery status is displayed in the visual form on the screen.

What is claimed is: 
     
       1. An integrated circuit, comprising:
 a power control unit to generate a status indicator if the charge on a battery decreases to a critical battery charge level, 
 a controller to include, 
 a power indication logic to, detect the occurrence of the status indicator, generate a request to power-on a first portion of the integrated circuit, wherein the request includes an identifier of the blocks in the first portion, send a request to power-on the first portion in response to detecting the status indicator, cause the critical battery status data stored in a memory to be transferred to a static memory, and 
 wherein the controller is a processor configured to execute code that causes:
 a display driver to write configuration values into one or more configuration registers in response to receiving a signal from the power indication logic; 
 
 
       a display controller to,
 determine that the critical battery status data is to be retrieved from the static memory based on the configuration values, 
 retrieve the critical battery status data from the static memory, and 
 render the critical battery status data in a visual form on a display, 
 wherein the first portion to include the static memory and the display controller. 
 
     
     
       2. The integrated circuit of  claim 1 , the static memory further comprises a control unit and one or more memory blocks, wherein the critical battery status data is stored in the one or more memory blocks. 
     
     
       3. The integrated circuit of  claim 1 , the one or more configuration registers include a first register, wherein the first register includes a power indication bit (PIB), static random access memory identifier (SRAM ID) field, start address (STRT ADDR) field, and an end address (END ADDR) field, wherein the PIB is configured with a first value, SRAM ID field is configured with an identifier of the static memory, STRT ADDR is configured with a starting address of the memory blocks from which the critical battery status data is to be retrieved, and the END ADDR field is configured with a last address of the memory blocks storing the critical battery status data. 
     
     
       4. The integrated circuit of  claim 3 , wherein storing the first value in the PIB is to indicate that the configuration values stored in the SRAM ID field, STRT ADDR field, and END ADDR field are valid. 
     
     
       5. The integrated circuit of  claim 3 , wherein storing a second value in the PIB is to indicate that one or more values stored in the SRAM ID field, STRT ADDR field, and END ADDR field are invalid. 
     
     
       6. The integrated circuit of  claim 5 , wherein the display controller to store the critical battery status data in a frame buffer after retrieving the critical battery status data from the memory blocks of the static memory before displaying the visual form on the display screen. 
     
     
       7. The integrated circuit of  claim 6  the display controller further comprises a control unit, wherein the control unit to render the critical battery status data, in a visual form, on a display. 
     
     
       8. A method in an integrated circuit, comprising:
 generating a status indicator in response to detecting a critical battery charge level is reached, 
 sending identifiers of one or more blocks to be powered-on in response to occurrence of the status indicator, 
 powering-on the one or more blocks based on the identifiers of the one or more blocks, wherein the one or more blocks include a static memory block and a display unit, 
 storing critical battery status data in the static memory block, wherein the static memory block is one of the one or more blocks which is powered-on, 
 configuring a first register to cause the critical battery status data to be retrieved from the static memory block, wherein configuring the first register further includes, configuring a power indication bit of the first register with a first value to indicate that configuration values in other fields of the first register are valid, configuring a static memory identifier field with an identifier of the static memory in which the critical battery status data is stored, wherein the other fields include the static memory field, configuring a start address and an end address field, respectively, with a starting address and a last address of memory blocks in which the critical battery status is stored, 
 configuring a power indication bit of a second register with a second value to indicate that configuration values in other fields of the second register are invalid, wherein the other fields include a field to store an identifier of a dynamic memory, 
 retrieving the critical battery status data based on the starting and last address and storing the critical battery status data into a frame buffer, 
 displaying a battery status in a visual form to indicate that a battery is being charged while substantial portion including a host processor is powered-down. 
 
     
     
       9. The method of  claim 8  comprises displaying a battery symbol on the display screen to indicate to a user that the battery is charging. 
     
     
       10. The method of  claim 8  further comprises checking a charge level on the battery at regular intervals and powering-on the substantial portion in response to receiving an input from the user. 
     
     
       11. The method of  claim 10  comprises powering-on at least the host processor, a dynamic memory block, and a system agent in response to receiving the input from the user.