Semiconductor memory device and data erasing method

Abstract

A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cells that are disposed in a second layer above the first layer; and 
 a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein. 
 
     
     
       2. The device according to  claim 1 , wherein a total number of first memory cells that failed is counted and compared against a first number to determine if the erasing operation should be repeated for the first memory cells, and a total number of second memory cells that failed is counted and compared against a second number to determine if the erasing operation should be repeated for the second memory cells. 
     
     
       3. The device according to  claim 2 , wherein the first and second numbers are different. 
     
     
       4. The device according to  claim 3 , further comprising:
 a plurality of word lines, each commonly connected to a different one of the memory cells in each memory string. 
 
     
     
       5. The device according to  claim 4 , wherein the verifying operation is performed on the memory cells, one group at a time, and a count of failed memory cells is stored separately for each layer. 
     
     
       6. The device according to  claim 5 , further comprising:
 a first bit line connected to a first end of the first memory string in each of the first and second groups; 
 a second bit line connected to a first end of the second memory string in each of the first and second groups; 
 a first source line connected to second ends of the first and second memory strings in the first group; and 
 a second source line connected to second ends of the first and second memory strings in the second group. 
 
     
     
       7. The device according to  claim 4 , wherein the verifying operation is performed on the memory cells, one layer at a time, and a total count of failed memory cells in the layer is stored. 
     
     
       8. The device according to  claim 7 , further comprising:
 a first bit line connected to first ends of the first and second memory strings in the first group; 
 a second bit line connected to first ends of the first and second memory strings in the second group; 
 a first source line connected to a second end of the first memory string in each of the first and second groups; and 
 a second source line connected to a second end of the second memory string in each of the first and second groups. 
 
     
     
       9. The device according to  claim 2 , wherein the controller selects a first increased erase voltage for a repeat erasing operation to be carried out on the memory cells in the first layer and a second increased erase voltage higher than the first increased erase voltage for a repeat erasing operation to be carried out on the memory cells in the second layer. 
     
     
       10. The device according to  claim 9 , wherein the controller is configured to control the difference between the first and second increased erase voltages to become smaller as the number of accumulated erasures on the memory cells increase. 
     
     
       11. The device according to  claim 1 , further comprising:
 a plurality of word lines, including first and second word lines, each commonly connected to a different one of the memory cells in each memory string, 
 wherein the erasing operation includes first through fourth erasing operations carried out in sequence, the first erasing operation being performed on the memory cells in the second layer connected to the second word line, the second erasing operation then being performed on the memory cells in the first layer connected to the second word line, the third erasing operation then being performed on the memory cells in the second layer connected to the first word line, and the fourth erasing operation then being performed on the memory cells in the first layer connected to the first word line. 
 
     
     
       12. A method of performing an erasing operation on a semiconductor memory device including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cells that are disposed in a second layer above the first layer, said method comprising:
 applying an erase voltage on the memory cells to erase data stored in the memory cells; and 
 performing a verifying operation to determine on a layer by layer basis whether the memory cells failed to erase data stored therein. 
 
     
     
       13. The method according to  claim 12 , further comprising:
 during the verifying operation, counting a first total number of first memory cells that failed and comparing the first total number against a first number to determine if a higher erase voltage should be applied to the first memory cells, and counting a second total number of second memory cells that failed the verifying operation and comparing the second total number against a second number to determine if a higher erase voltage should be applied to the second memory cells. 
 
     
     
       14. The method according to  claim 13 , wherein the first and second numbers are different. 
     
     
       15. The method according to  claim 14 , further comprising:
 selecting a first increased erase voltage as the higher erase voltage to be applied to the first memory cells and a second increased erase voltage, that is different from the first increased erase voltage, as the higher erase voltage to be applied to the second memory cells. 
 
     
     
       16. The method according to  claim 15 , wherein said selecting is carried out according to the number of accumulated erasures on the memory cells, such that the difference between the first and second increased erase voltages is smaller as the number of accumulated erasures on the memory cells increase. 
     
     
       17. The method according to  claim 12 , wherein the verifying operation is performed on the memory cells, one group at a time, and a count of failed memory cells is stored separately for each layer. 
     
     
       18. The method according to  claim 12 , wherein the verifying operation is performed on the memory cells, one layer at a time, and a total count of failed memory cells in the layer is stored. 
     
     
       19. The method according to  claim 12 , wherein different erase voltages are applied to the memory cells to erase the data stored in the memory cells. 
     
     
       20. The method according to  claim 12 , wherein the semiconductor memory device further includes a plurality of word lines, including first and second word lines, each commonly connected to a different one of the memory cells in each memory string, and said applying includes the following steps carried out in sequence:
 applying an erase voltage on the memory cells in the second layer connected to the second word line, 
 applying an erase voltage on the memory cells in the first layer connected to the second word line, 
 applying an erase voltage on the memory cells in the second layer connected to the first word line, and 
 applying an erase voltage on the memory cells in the first layer connected to the first word line.