High voltage comparison circuit

Abstract

A high voltage comparison circuit includes an input stage generating an intermediate signal as a result of a comparison between an input signal and a first voltage reference and an output stage configured to generate an output signal referenced to a second voltage reference (different from the first voltage reference) in response to the intermediate signal.

The invention claimed is: 
     
       1. A high voltage comparison circuit, comprising:
 an input stage arranged between a supply voltage node and a first voltage reference node, said input stage configured to receive an input voltage signal and comprising a voltage comparator configured to provide an intermediate signal at an output terminal of the input stage as a result of a comparison between the input voltage signal and a first voltage at said first voltage reference node; and 
 an output stage arranged between said supply voltage node and a second voltage reference node configured to receive a second voltage different from said first voltage, said output stage configured to receive said intermediate signal and to provide an output voltage signal which is in response to said intermediate signal, 
 wherein said voltage comparator comprises:
 a first-type MOSFET transistor and a second n-type MOSFET transistor having their gate terminals connected together to a common-gate node, said second n-type MOSFET transistor being configured as a diode, and 
 a first resistor and a second resistor each connected in series with a source terminal of the first and second n-type MOSFET transistors, respectively, and 
 
 wherein said input stage comprises:
 a voltage buffer through which the input voltage signal is received, and 
 a pass-gate configured to receive the input voltage signal before the input signal is received by said voltage buffer, wherein said pass-gate comprises an n-type MOSFET transistor having a gate terminal connected to the common-gate node. 
 
 
     
     
       2. The high voltage comparison circuit according to  claim 1 , wherein said voltage comparator is a hysteresis voltage comparator. 
     
     
       3. The high voltage comparison circuit according to  claim 2 , wherein said hysteresis voltage comparator has a hysteresis range given by a voltage drop across a resistor. 
     
     
       4. A high voltage comparison circuit, comprising:
 an input stage arranged between a supply voltage node and a first voltage reference node, said input stage configured to receive an input voltage signal and comprising a voltage comparator configured to provide an intermediate signal at an output terminal of the input stage as a result of a comparison between the input voltage signal and a first voltage at said first voltage reference node; and 
 an output stage arranged between said supply voltage node and a second voltage reference node configured to receive a second voltage different from said first voltage, said output stage configured to receive said intermediate signal and to provide an output voltage signal which is in response to said intermediate signal, 
 wherein said input stage comprises a voltage buffer through which the input voltage signal is received, 
 wherein said voltage comparator is a hysteresis voltage comparator, 
 wherein said hysteresis voltage comparator further comprises:
 a first n-type MOSFET transistor and a second n-type MOSFET transistor having their gate terminals connected together to a common-gate node, said second n-type MOSFET transistor being configured as a diode, 
 a first resistor and a second resistor each connected in series with a source terminal of the first and second n-type MOSFET transistors, respectively, 
 a third resistor coupled in series with said second resistor, and 
 a first switch driven by said intermediate signal and configured to manage flow of a bias current toward said third resistor. 
 
 
     
     
       5. The high voltage comparison circuit according to  claim 1 , wherein said voltage buffer comprises:
 a first p-type MOSFET transistor configured as a source-follower and arranged between the first resistor and the first voltage reference node, said first p-type MOSFET transistor having a gate terminal drive by the input voltage signal. 
 
     
     
       6. The high voltage comparison circuit according to  claim 1 , further comprising a first Zener diode coupled between the supply voltage node and the output terminal of the input stage. 
     
     
       7. A high voltage comparison circuit, comprising:
 an input stage arranged between a supply voltage node and a first voltage reference node, said input stage configured to receive an input voltage signal and comprising a voltage comparator configured to provide an intermediate signal at an output terminal of the input stage as a result of a comparison between the input voltage signal and a first voltage at said first voltage reference node; and 
 an output stage arranged between said supply voltage node and a second voltage reference node configured to receive a second voltage different from said first voltage, said output stage configured to receive said intermediate signal and to provide an output voltage signal which is in response to said intermediate signal, 
 wherein said input stage comprises a voltage buffer through which the input voltage signal is received, 
 wherein said voltage comparator comprises:
 a first-type MOSFET transistor and a second n-type MOSFET transistor having their gate terminals connected together to a common-gate node, said second n-type MOSFET transistor being configured as a diode, 
 a first resistor and a second resistor each connected in series with a source terminal of the first and second n-type MOSFET transistors, respectively, and 
 a first diode and a second diode oppositely connected between source terminals of the first and second n-type MOSFET transistors. 
 
 
     
     
       8. A circuit, comprising:
 a supply voltage node configured to receive a supply voltage; 
 a first reference voltage node configured to receive a first reference voltage; 
 a second reference voltage node configured to receive a second reference voltage; 
 a first MOS transistor of a first conductivity type configured to receive an input signal and having a drain terminal coupled to the first reference voltage node; 
 a second MOS transistor of the first conductivity type having gate and drain terminals coupled to the first reference voltage node; 
 a third MOS transistor of a second conductivity type having a drain terminal, a source terminal and a gate terminal; 
 a first resistor network coupled between the source terminal of the third MOS transistor and a source terminal of the first MOS transistor; 
 a fourth MOS transistor of the second conductivity type having a drain terminal, a source terminal and a gate terminal, wherein the gate terminal of the fourth MOS transistor is coupled to the gate terminal of the third MOS transistor; 
 a second resistor network coupled between the source terminal of the fourth MOS transistor and a source terminal of the second MOS transistor; 
 a fifth MOS transistor of the second conductivity type having a gate terminal coupled to the drain terminal of the third MOS transistor and having a drain terminal coupled to an intermediate node in the second resistor network; and 
 a sixth MOS transistor of the second conductivity type have a gate terminal coupled to the drain terminal of the third MOS transistor and having a source terminal coupled to the supply voltage node and a drain terminal coupled to the second reference voltage node. 
 
     
     
       9. The circuit of  claim 8 , further comprising a pass gate transistor coupled between an input node configured to receive the input signal and a gate terminal of the first MOS transistor, wherein a control terminal of the pass gate transistor is coupled to the gate terminals of the third and fourth MOS transistors. 
     
     
       10. The circuit of  claim 8 , further comprising a zener diode coupled between the drain terminal of the third MOS transistor and the supply voltage node. 
     
     
       11. The circuit of  claim 8 , wherein the gate terminal of the fourth transistor is coupled to the drain terminal of the fourth transistor. 
     
     
       12. The circuit of  claim 8 , further comprising a logic-NOT gate having an input coupled to the drain terminal of the sixth MOS transistor. 
     
     
       13. The circuit of  claim 8 , further comprising a bias circuit configured to supply bias currents to the drain terminals of the third and fourth MOS transistors and supply bias currents to the source terminals of the fifth and sixth MOS transistors. 
     
     
       14. The circuit of  claim 8 , further comprising a zener diode coupled between the drain terminal of the sixth MOS transistor and the second reference voltage node. 
     
     
       15. The circuit of  claim 8 , further comprising:
 a first bias circuit configured to source bias current to the source terminal of the sixth MOS transistor; and 
 a second bias circuit configured to sink bias current from the drain terminal of the sixth MOS transistor. 
 
     
     
       16. The circuit of  claim 8 , wherein the second resistor network comprises:
 a first resistor; and 
 a second resistor coupled in series with the first resistor at the intermediate node. 
 
     
     
       17. The circuit of  claim 16 , wherein second resistor comprises: a third and fourth resistors coupled in series, and wherein the first resistor network comprises a fifth resistor having a resistance equal to a resistance of the third resistor.