Low phase noise technique for a crystal oscillator circuit

Abstract

In aspects of a low phase noise technique for use with a crystal oscillator, a bias control circuit sets a bias voltage on the gate of a first transistor needed to sink or source an amount of current corresponding to a sensed common mode signal. The sensed common mode signal is sensed with a common mode sense circuit that is coupled across two ports of the crystal oscillator, and current is provided by a current source. The bias voltage is set by a bias controller that uses a second transistor coupled to the common mode sense circuit and the first transistor.

What is claimed is: 
     
       1. An electronic circuit for controlling a crystal oscillator, comprising:
 a common mode sense circuit coupled to two ports of the crystal oscillator and configured to sense a common mode signal across the two ports; 
 a first transistor coupled to the two ports of the crystal oscillator; and 
 a bias controller configured to set a bias voltage on a gate of the first transistor based on the sensed common mode signal, the bias controller including a second transistor, a gate of the second transistor being coupled to the common mode sense circuit, and a source of the second transistor being resistively coupled to the gate of the first transistor. 
 
     
     
       2. The electronic circuit as recited in  claim 1 , wherein the common mode sense circuit comprises a pair of equally-valued resistors. 
     
     
       3. The electronic circuit as recited in  claim 1 , wherein the common mode sense circuit, the first transistor, and the bias controller comprise a first chip and the crystal oscillator comprises a second chip. 
     
     
       4. The electronic circuit as recited in  claim 1 , wherein the first transistor is further coupled to a current source. 
     
     
       5. The electronic circuit as recited in  claim 4 , wherein the bias voltage is further set according to an amount of current to or from the current source. 
     
     
       6. The electronic circuit as recited in  claim 1 , wherein the gate of the first transistor is further coupled with a capacitor to clock distribution circuitry. 
     
     
       7. The electronic circuit as recited in  claim 6 , wherein the clock distribution circuitry generates clocks for processing of signals compliant with an IEEE 802.11ac standard. 
     
     
       8. The electronic circuit as recited in  claim 1 , wherein at least one of the first transistor and the second transistor is a field effect transistor (FET). 
     
     
       9. The electronic circuit as recited in  claim 1 , wherein the source of the second transistor is further coupled to a grounded capacitor and a grounded resistor. 
     
     
       10. The electronic circuit as recited in  claim 1 , wherein the common mode sense circuit, the first transistor, and the bias controller are embodied on a system-on-chip (SoC). 
     
     
       11. A method for controlling a crystal oscillator, comprising:
 coupling a common mode sense circuit to two ports of the crystal oscillator; 
 sensing a common mode signal across the two ports of the crystal oscillator; 
 coupling a first transistor to the two ports of the crystal oscillator; 
 coupling a gate of a second transistor in a bias controller to the common mode sense circuit; 
 coupling a source of the second transistor in the bias controller to a gate of the first transistor; and 
 setting a bias voltage with the bias controller on the gate of the first transistor based on the sensed common mode signal. 
 
     
     
       12. The method as recited in  claim 11 , wherein the common mode sense circuit comprises a pair of equally-valued resistors. 
     
     
       13. The method as recited in  claim 11 , wherein the common mode sense circuit, the first transistor, and the bias controller comprise a first chip and the crystal oscillator comprises a second chip. 
     
     
       14. The method as recited in  claim 11 , further comprising coupling the first transistor to a current source, and wherein the setting of the bias voltage is further according to an amount of current to or from the current source. 
     
     
       15. The method as recited in  claim 11 , further comprising coupling the gate of the first transistor with a capacitor to clock distribution circuitry. 
     
     
       16. The method as recited in  claim 11 , wherein at least one of the first transistor and the second transistor is a field effect transistor (FET). 
     
     
       17. The method as recited in  claim 11 , further comprising coupling the source of the second transistor to a grounded capacitor and a grounded resistor. 
     
     
       18. A system, comprising:
 a crystal oscillator; 
 a common mode sense circuit coupled to two ports of the crystal oscillator and configured to sense a common mode signal across the two ports; 
 a first transistor coupled to the two ports of the crystal oscillator; and 
 a bias controller comprising a second transistor with a gate coupled to the common mode sense circuit and a source coupled to the gate of the first transistor, and the bias controller configured to set a bias voltage on the gate of the first transistor based on the sensed common mode signal. 
 
     
     
       19. The system as recited in  claim 18 , wherein the common mode sense circuit, the first transistor, and the bias controller comprise a first chip and the crystal oscillator comprises a second chip. 
     
     
       20. The system as recited in  claim 18 , further comprising a current source coupled to the first transistor, and wherein the bias voltage is further set according to an amount of current to or from the current source.