Cascaded digital filters with reduced latency

Abstract

A filter and method for filtering a signal are disclosed. The filter is equivalent to a plurality of bi-quad filters connected in series, and is implemented on a digital processor that receives a sequence of signal values at a sampling rate characterized by a sampling interval and generates a filtered signal value upon receiving each received signal value. The filter has a latency that is less than the sampling interval. The filtered values can be generated by adding a term to a received signal value and multiplying the sum by a gain constant that depends on the filter constants. The added term does not depend on the current received signal value. The filter can be implemented in fixed-point integer arithmetic.

What is claimed is: 
     
       1. A filter comprising any positive integer number of poles and zeros where this filter is equivalent to a plurality of bi-quad and/or bilinear filters connected in series, said filter being implemented on a digital processor that receives a sequence of signal values at a sampling rate characterized by a sampling interval and generates a filtered signal value upon receiving each received signal value, said filter having a latency that is less than said sampling interval. 
     
     
       2. The filter of  claim 1  wherein said filter is characterized by a number of parameters and wherein said latency is independent of said number of parameters. 
     
     
       3. The filter of  claim 1  wherein said processor generates each filtered signal value by adding a term to a received signal value and multiplying the sum by a gain constant that depends on said constants, wherein said term does not depend on said received signal value. 
     
     
       4. The filter of  claim 3  wherein said term depends on previously received signal values and constants characterizing said series-connected bi-quad filters. 
     
     
       5. The filter of  claim 1  wherein said plurality of bi-quad filters comprises a plurality of unit direct feedthrough gain bi-quad filters flowed by a gain stage. 
     
     
       6. The filter of  claim 5  wherein a plurality of the unit direct feedthrough gain bi-quad filters implements a bilinear filter. 
     
     
       7. The filter of  claim 3  wherein said processor generates said term utilized to compute the next filtered value prior to receiving the next signal value. 
     
     
       8. The filter of  claim 3  wherein said processor utilizes fixed-point integer arithmetic to compute said term. 
     
     
       9. The filter of  claim 8  wherein said bi-quad filter comprises a filter that provides a frequency notch or resonance at a predetermined frequency, said sampling rate being high compared to said predetermined frequency, and wherein said term is computed by multiplying one of said constants by a scaling factor prior to computing said term, said scaling factor being chosen to reduce round-off error in said term. 
     
     
       10. The filter of  claim 1  wherein said filter is implemented using a state space form. 
     
     
       11. The filter of  claim 1  wherein said filter is implemented using a transfer function form. 
     
     
       12. The filter method of  claim 8  wherein said bi-quad filter comprises a filter that provides a shaping of the frequency response in a desired frequency range, said sampling rate being high compared to said desired frequency range, and wherein said term is computed by multiplying one of said constants by a scaling factor prior to computing said term, said scaling factor being chosen to reduce round-off error in said term. 
     
     
       13. A method for filtering a signal to generate a filtered signal that approximates the results of filtering said signal through a series connected string of bi-quad or bilinear filters, said method comprising:
 receiving a sequence of signal values at a sampling rate characterized by a sampling interval; 
 generating a filtered signal value corresponding to each received signal value by adding a term to said received signal value and scaling the result to provide said filtered signal value, said term being independent of said corresponding received signal value; 
 outputting said filtered signal value; and 
 generating said term corresponding to said next signal value prior to receiving said next signal value. 
 
     
     
       14. The method of  claim 13  wherein said term depends on previously received signal values and constants characterizing said series-connected bi-quad filters. 
     
     
       15. The method of  claim 13  wherein generating said term comprises only arithmetic operations in fixed-point integer arithmetic. 
     
     
       16. The method of  claim 15  wherein said bi-quad filter comprises a filter that provides a frequency notch or resonance at a predetermined frequency, said sampling rate being high compared to said predetermined frequency, and wherein said term is computed by multiplying one of said constants by a scaling factor prior to computing said term, said scaling factor being chosen to reduce round-off error in said term. 
     
     
       17. The method of  claim 15  wherein said bi-quad filter comprises a filter that provides a shaping of the frequency response in a desired frequency range, said sampling rate being high compared to said desired frequency range, and wherein said term is computed by multiplying one of said constants by a scaling factor prior to computing said term, said scaling factor being chosen to reduce round-off error in said term. 
     
     
       18. The method of  claim 13  wherein a plurality of the unit direct feedthrough gain bi-quad filters implements a bilinear filter. 
     
     
       19. The method of  claim 13  wherein said filter is implemented using a state space form. 
     
     
       20. The method of  claim 13  wherein said filter is implemented using a transfer function form.