Push-pull voltage driver with low static current variation

Abstract

A push-pull driver is provided with a differential amplifier that amplifies a difference between an input voltage and an output voltage to drive a bias node coupled to a diode-connected bias transistor. The push-pull driver is configured to control the drain-to-source voltage for a source-follower output transistor having its gate tied to a gate for the diode-connected bias transistor to be proportional to the drain-to-source voltage for the diode-connected bias transistor. This proportionality prevents excessive static current variation that would otherwise be present in the source-follower output transistor.

We claim: 
     
       1. A circuit, comprising:
 a differential amplifier configured to drive a bias node based on a comparison of an output voltage at an output node and an input voltage; 
 a first diode-connected bias transistor having a first terminal coupled to the bias node; 
 a first source-follower output transistor having a first terminal coupled to the output node and a gate coupled to a gate of the first diode-connected bias transistor; 
 a first cascode transistor coupled to a second terminal of the first source-follower output transistor; and 
 at least one first diode coupled to the output node, wherein the at least one first diode includes a terminal coupled to a gate of the first cascode transistor. 
 
     
     
       2. The circuit of  claim 1 , wherein the at least one first diode comprises a first diode-connected transistor having a first terminal coupled to the output node and a second diode-connected transistor having a first terminal coupled to a second terminal of the first diode-connected transistor, and wherein a gate of the second diode-connected transistor is coupled to the gate of the cascode transistor. 
     
     
       3. The circuit of  claim 2 , wherein the first diode-connected transistor, the second diode-connected transistor, and the cascode transistor are NMOS transistors. 
     
     
       4. The circuit of  claim 2 , wherein the first diode-connected transistor, the second diode-connected transistor, and the cascode transistor are PMOS transistors. 
     
     
       5. The circuit of  claim 2 , further comprising a current source configured to drive a bias current into a second terminal of the second diode-connected transistor. 
     
     
       6. The circuit of  claim 1 , further comprising:
 a second diode-connected bias transistor having a terminal coupled to the bias node; 
 a second source-follower output transistor having a first terminal coupled to the output node and a gate coupled to a gate of the second diode-connected bias transistor; 
 a second cascode transistor coupled to a second terminal of the second source-follower output transistor; and 
 at least one second diode coupled to the output node, wherein the at least one second diode includes a terminal coupled to a gate of the second cascode transistor. 
 
     
     
       7. The circuit of  claim 1 , further comprising:
 a current source configured to drive a current into a second terminal of the first diode-connected bias transistor. 
 
     
     
       8. The circuit of  claim 1 , further comprising:
 a current source; and 
 a second cascode transistor having a first terminal coupled to a second terminal of the first diode-connected bias transistor and a second terminal coupled to the current source, wherein a gate of the first diode-connected bias transistor couples to the second terminal of the second cascode transistor. 
 
     
     
       9. The circuit of  claim 1 , wherein the first diode-connected bias transistor, the first cascode transistor, and the first source-follower output transistor all comprise NMOS transistors. 
     
     
       10. The circuit of  claim 1 , wherein the first diode-connected bias transistor, the first cascode transistor, and the first source-follower output transistor all comprise PMOS transistors. 
     
     
       11. The circuit of  claim 1 , wherein the differential amplifier is configured to drive bias node so that the output voltage equals the input voltage. 
     
     
       12. The circuit of  claim 1 , wherein the first diode-connected bias transistor is configured to have a drain-to-source voltage that equals a drain-to-source voltage for the first source-follower output transistor. 
     
     
       13. The circuit of  claim 1 , wherein the first diode-connected transistor is configured to have a drain-to-source voltage that is proportional to a drain-to-source voltage for the first source-follower output transistor. 
     
     
       14. A method
 biasing a first terminal of a diode-connected bias transistor with a voltage equaling an amplified difference between an output voltage and an input voltage to bias a gate voltage for the first diode-connected bias transistor; 
 driving a gate of a source-follower output transistor having a first terminal coupled to the output node with the biased gate voltage to adjust the output voltage; 
 biasing at least one diode with the adjusted output voltage to produce a diode voltage; and 
 driving a gate of a cascade transistor coupled to a second terminal of the source-follower output transistor with the diode voltage. 
 
     
     
       15. The method of  claim 14 , wherein biasing the at least one diode comprises biasing a pair of diode-connected transistors such that the diode voltage equals the output voltage plus twice a threshold voltage for each of the diode-connected transistors in the pair. 
     
     
       16. The method of  claim 14 , wherein biasing the at least one diode comprises biasing a single diode-connected transistor such that the diode voltage equals the output voltage plus a threshold voltage for the single diode-connected transistor. 
     
     
       17. The method of  claim 14 , further comprising driving a bias current into a second terminal of the diode-connected bias transistor. 
     
     
       18. A circuit, comprising:
 a differential amplifier configured to drive a bias node based on a comparison of an output voltage at an output node and an input voltage; 
 a first diode-connected bias transistor having a source coupled to the bias node; 
 a first source-follower output transistor having a source terminal coupled to the output node and a gate coupled to a gate of the first diode-connected bias transistor; and 
 means for maintaining a drain-to-source voltage for the first source-follower output transistor to be proportional to a drain-to-source voltage for the first diode-connected bias transistor. 
 
     
     
       19. The circuit of  claim 18 , wherein the means is configured so that the drain-to-source voltage for the first source-follower transistor equals the drain-to-source voltage for the first diode-connected bias transistor. 
     
     
       20. The circuit of  claim 18 , further comprising:
 a second diode-connected bias transistor having a source coupled to the bias node; and 
 a second source-follower output transistor having a source terminal coupled to the output node and a gate coupled to a gate of the second diode-connected bias transistor.