Driver output with dynamic switching bias

Abstract

A circuit of an output stage of a push-pull driver having dynamic biasing may include a stacked configuration of field effect transistors (PFETs) having a first PFET, a second PFET, and a third PFET, whereby the first PFET is connected to a first supply voltage, the third PFET is connected to an output of a switchable voltage bias generator circuit, and the second PFET is electrically connected between the first PFET and the third PFET. A transmission gate may be connected to a second supply voltage, whereby the transmission gate electrically connects the second supply voltage to an electrical connection between the first PFET and the second PFET based on a first operating state for preventing a voltage breakdown condition associated with the stacked configuration of PFETs. The third PFET is bias controlled via the switching of the output of the switchable voltage bias generator circuit.

What is claimed is: 
     
       1. A circuit of an output stage of a push-pull driver having dynamic biasing, the circuit comprising:
 a first stacked configuration of p-type field effect transistors (PFETs) having a first PFET, a second PFET, and a third PFET, wherein the first PFET is connected to a first supply voltage, the third PFET is connected to an output of a first switchable voltage bias generator circuit, and the second PFET is electrically connected between the first PFET and the third PFET; and 
 a first transmission gate connected to a second supply voltage, wherein the first transmission gate electrically connects the second supply voltage to an electrical connection between the first PFET and the second PFET based on a first operating state for preventing a first voltage breakdown condition associated with the first stacked configuration of PFETs, and wherein the third PFET is bias controlled via the switching of the output of the first switchable voltage bias generator circuit. 
 
     
     
       2. The circuit of  claim 1 , further comprising:
 a second stacked configuration of n-type field effect transistors (NFETs) having a first NFET, a second NFET, and a third NFET, wherein the first NFET is connected to a ground voltage, the third NFET is connected to the output of the first switchable voltage bias generator circuit, and the second NFET is electrically connected between the first NFET and the third NFET; and 
 a second transmission gate connected to a third supply voltage, wherein the second transmission gate electrically connects the third supply voltage to an electrical connection between the first NFET and the second NFET based on a second operating state for preventing a second voltage breakdown condition associated with the second stacked configuration of NFETs, and wherein the third NFET in the second stacked configuration of n-type NFETs is bias controlled via the switching of the output of the first switchable voltage bias generator circuit. 
 
     
     
       3. The circuit of  claim 2 , wherein the first PFET, the second PFET, the third PFET, the first NFET, the second NFET, the third NFET, the first transmission gate, and the second transmission gate each comprise a 1.5V FET device and, wherein the first supply voltage comprises about 3.3V. 
     
     
       4. The circuit of  claim 2 , wherein the first supply voltage comprises about 3.3V, the second supply voltage comprises about 1.8V, and the third supply voltage comprises about 1.5V. 
     
     
       5. The circuit of  claim 2 , wherein the first transmission gate comprises an n-type field effect transistor (NFET), and wherein the second transmission gate comprises a p-type field effect transistor (PFET). 
     
     
       6. The circuit of  claim 1 , wherein the first voltage breakdown condition comprises at least one of a dielectric breakdown condition and a parasitic bipolar breakdown condition associated with the first stacked configuration of PFETs. 
     
     
       7. The circuit of  claim 2 , wherein the second voltage breakdown condition comprises at least one of a dielectric breakdown condition and a parasitic bipolar breakdown condition associated with the second stacked configuration of NFETs. 
     
     
       8. The circuit of  claim 2 , wherein the first switchable voltage bias generator circuit comprises a 1.5V output during the first operating state, and wherein the first switchable voltage bias generator circuit comprises a 1.8V output during the second operating state. 
     
     
       9. The circuit of  claim 2 , further comprising a control input, wherein during the first operating state the control input receives about a 1.5V input that controls the second transmission gate to an OFF state, and wherein during the second operating state the control input receives about a 0V input that controls the second transmission gate to an ON state. 
     
     
       10. The circuit of  claim 9 , further comprising a second switchable voltage bias generator circuit that controls the first transmission gate, wherein during the first operating state the second switchable voltage bias generator circuit turn the first transmission gate to an ON state, and wherein during the second operating state the second switchable voltage bias generator circuit turn the first transmission gate to an OFF state. 
     
     
       11. The circuit of  claim 10 , wherein the second switchable voltage bias generator circuit comprises:
 a third stacked configuration of field effect transistors (FETs) including an output of the second switchable voltage bias generator circuit, wherein during both the first operating state and the second operating state the third stacked configuration of FETs are in an ON state; and 
 a fourth stacked configuration of field effect transistors (FETs), wherein during the first operating state the fourth stacked configuration of FETs are in an ON state, and wherein during the second operating state the fourth stacked configuration of FETs are in an OFF state. 
 
     
     
       12. The circuit of  claim 11 , wherein the third stacked configuration comprises:
 a fourth PFET, a fifth PFET and a fourth NFET, wherein the fourth PFET is connected to the first supply voltage, and the electrical connection between the fifth PFET and the fourth NFET forms the output of the second switchable voltage bias generator circuit; and 
 a transmission gate pair connected to the second supply voltage, the transmission gate pair electrically connecting the second supply voltage to an electrical connection located between the fourth NFET and a first terminal of a load resistor, wherein the transmission gate pair prevents a third voltage breakdown condition associated with the third stacked configuration of FETs. 
 
     
     
       13. The circuit of  claim 12 , wherein the fourth stacked configuration comprises:
 a fifth NFET, a sixth NFET and a seventh NFET, wherein the fifth NFET is connected to ground, the seventh NFET is connected to a second terminal of the load resistor, and the sixth NFET is connected between the fifth NFET and the seventh NFET; and 
 a third transmission gate connected to the third supply voltage, the third transmission gate connecting the third supply voltage to an electrical connection located between the fifth NFET and the sixth NFET, wherein the third transmission gate prevents a fourth voltage breakdown condition associated with the fourth stacked configuration of FETs. 
 
     
     
       14. The circuit of  claim 12 , wherein the transmission gate pair comprises two n-type field effect transistors (NFETs). 
     
     
       15. The circuit of  claim 13 , wherein the third transmission gate comprises a p-type field effect transistor (PFET). 
     
     
       16. The circuit of  claim 12 , wherein the third voltage breakdown condition comprises at least one of a dielectric breakdown condition and a parasitic bipolar breakdown condition associated with the third stacked configuration of FETs. 
     
     
       17. The circuit of  claim 13 , wherein the fourth voltage breakdown condition comprises at least one of a dielectric breakdown condition and a parasitic bipolar breakdown condition associated with the fourth stacked configuration of FETs. 
     
     
       18. The circuit of  claim 13 , wherein the first switchable voltage bias generator circuit comprises:
 an NFET cascade connected between the second supply voltage, the output of the second switchable voltage bias generator circuit, and an output of the first switchable voltage bias generator circuit, wherein during the first operating state the output of the second switchable voltage bias generator circuit turns the NFET cascade to an OFF state, and during the second operating state the second switchable voltage bias generator circuit turn the NFET cascade to an ON state, wherein during the ON state the NFET cascade connects the second supply voltage to the output of the first switchable voltage bias generator circuit; 
 a PFET cascade connected between the third supply voltage, the output of the second switchable voltage bias generator circuit, and the control input, wherein during the first operating state the control input turns the PFET cascade to an ON state, and during the second operating state the control input turn the PFET cascade to an OFF state, wherein during the ON state the PFET cascade connects the third supply voltage to the output of the first switchable voltage bias generator circuit. 
 
     
     
       19. The circuit of  claim 18 , wherein the NFET cascade comprises an eighth NFET and a second resistor, wherein during the first operating state the eighth NFET is in an OFF state, and wherein during the second operating state the eighth NFET is in an ON state and connects the second supply voltage to the output of the first switchable voltage bias generator circuit, and wherein the PFET cascade comprises a sixth PFET and a third resister, wherein during the first operating state the sixth PFET is in an ON state, and wherein during the second operating state the sixth PFET is in an OFF state and connects the third supply voltage to the output of the first switchable voltage bias generator circuit. 
     
     
       20. The circuit of  claim 19 , wherein the output of the first switchable voltage bias generator circuit includes about a 1.5V output during the first operating state and about a 1.8V output during the second operating state.