US9419162B2ActiveUtilityA1

Array sensor apparatus and forming method thereof

81
Assignee: SHANGHAI OXI TECH CO LTDPriority: Jun 23, 2014Filed: Sep 23, 2014Granted: Aug 16, 2016
Est. expiryJun 23, 2034(~7.9 yrs left)· nominal 20-yr term from priority
Inventors:Weiping Lin
H10F 77/1662H10F 77/334H10F 77/122H10F 77/12H10F 39/198H10F 39/016H10F 77/1642H01L 31/02164H01L 27/14678G06K 9/00053H01L 31/03762H01L 31/028G06K 9/0002H01L 31/03682H01L 31/032H01L 27/14692G06V 40/1329G06V 40/1306
81
PatentIndex Score
3
Cited by
5
References
11
Claims

Abstract

An array sensor apparatus and forming method thereof, wherein the array sensor comprises: a driving circuit and a sensor circuit, wherein the driving circuit and the sensor circuit are formed on the same substrate surface, the sensor circuit comprises a pixel cell array including pixel cells and driving lines connected with the pixel cells, output ends of the driving circuit are connected to the driving lines of the sensor circuit, the driving circuit comprises a first transistor, and the pixel cell comprises a second transistor. In the array sensor apparatus of the present disclosure, the driving circuit and the sensor circuit are formed on the same substrate surface, thus occupying less area. Reliability may be improved. Besides, the forming processes can be implemented simultaneously without additional processing steps.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. An array sensor, comprising:
 a driving circuit and a sensor circuit, wherein the driving circuit and the sensor circuit are configured onto a same substrate surface, the sensor circuit comprises a pixel cell array comprising pixel cells and driving lines connected with the pixel cells, output ends of the driving circuit are connected to the driving lines of the sensor circuit, the driving circuit comprises a first transistor, and the pixel cell comprises a second transistor; 
 wherein the first transistor comprises:
 a first conductive layer located on the substrate surface; 
 a first insulating layer overlaying the first conductive layer; 
 a first semiconductor layer located on a surface of the first insulating layer, wherein position of the first semiconductor corresponds to position of the first conductive layer; 
 a second conductive layer overlaying the first semiconductor layer, wherein the second conductive layer has a first opening which partially exposes a surface of the first semiconductor layer; 
 a second insulating layer overlaying the second conductive layer and filling up the first opening; and 
 a first barrier layer located on a surface of the second insulating layer, wherein position of the first barrier layer corresponds to position of the first opening; 
 
 and wherein the second transistor comprises:
 a third conductive layer located on the substrate surface; 
 a third insulating layer overlaying the third conductive layer; 
 a second semiconductor layer located on a surface of the third insulating layer, wherein position of the second semiconductor layer corresponds to position of the third conductive layer; 
 a fourth conductive layer overlaying the second semiconductor layer, wherein the fourth conductive layer has a second opening which partially exposes a surface of the second semiconductor layer; 
 a fourth insulating layer overlaying the fourth conductive layer and filling up the second opening; 
 a second barrier layer located on a surface of the fourth insulating layer, wherein position of the second barrier layer corresponds to position of the second opening; and 
 a conductive plug located in the third insulating layer, wherein a first surface of the conductive plug contacts with the second conductive layer, and a second surface of the conductive plug contacts with the third conductive layer. 
 
 
     
     
       2. The array sensor according to  claim 1 , wherein the driving circuit is located on a periphery region of the pixel cell array. 
     
     
       3. The array sensor according to  claim 1 , wherein the first barrier layer and the second barrier layer both comprise a light-block material. 
     
     
       4. The array sensor according to  claim 1 , wherein the first semiconductor layer comprises amorphous silicon, low temperature poly-silicon or oxide semiconductor, and the second semiconductor layer comprises amorphous silicon, low temperature poly-silicon or oxide semiconductor. 
     
     
       5. The array sensor according to  claim 1 , further comprising a system controller and a soft connector, wherein the driving circuit is electrically connected with the system controller through the soft connector. 
     
     
       6. An array sensor, comprising:
 a driving circuit and a sensor circuit, wherein the driving circuit and the sensor circuit are configured onto a same substrate surface, the sensor circuit comprises a pixel cell array comprising pixel cells and driving lines connected with the pixel cells, output ends of the driving circuit are connected to the driving lines of the sensor circuit, the driving circuit comprises a first transistor, and the pixel cell comprises a second transistor; 
 wherein the first transistor comprises:
 a first conductive layer located on the substrate surface; 
 a first insulating layer overlaying the first conductive layer; 
 a first semiconductor layer located on a surface of the first insulating layer, wherein position of the first semiconductor corresponds to position of the first conductive layer; 
 a second conductive layer overlaying the first semiconductor layer, wherein the second conductive layer has a first opening which partially exposes a surface of the first semiconductor layer; 
 a second insulating layer overlaying the second conductive layer and filling up the first opening; and 
 a first barrier layer located on a surface of the second insulating layer, wherein position of the first barrier layer corresponds to position of the first opening; 
 
 wherein the second transistor comprises:
 a third conductive layer located on the substrate surface; 
 a third insulating layer overlaying the third conductive layer; 
 a second semiconductor layer located on a surface of the third insulating layer, wherein position of the second semiconductor layer corresponds to position of the third conductive layer; 
 a fourth conductive layer overlaying the second semiconductor layer, wherein the fourth conductive layer has a second opening which partially exposes a surface of the second semiconductor layer; 
 a fourth insulating layer overlaying the fourth conductive layer and filling up the second opening; and 
 a second barrier layer located on a surface of the fourth insulating layer, wherein position of the second barrier layer corresponds to position of the second opening, and wherein the first barrier layer and the second barrier layer are both connected to a fixed electrical potential. 
 
 
     
     
       7. The array sensor according to  claim 6 , wherein the driving circuit is located on a periphery region of the pixel cell array. 
     
     
       8. The array sensor according to  claim 6 , further comprising a conductive plug located in the third insulating layer, wherein a first surface of the conductive plug contacts with the second conductive layer, and a second surface of the conductive plug contacts with the third conductive layer. 
     
     
       9. The array sensor according to  claim 6 , wherein the first barrier layer and the second barrier layer both comprise a light-block material. 
     
     
       10. The array sensor according to  claim 6 , wherein the first semiconductor layer comprises amorphous silicon, low temperature poly-silicon or oxide semiconductor, and the second semiconductor layer comprises amorphous silicon, low temperature poly-silicon or oxide semiconductor. 
     
     
       11. The array sensor according to  claim 6 , further comprising a system controller and a soft connector, wherein the driving circuit is electrically connected with the system controller through the soft connector.

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