LDO regulator with improved load transient performance for internal power supply

Abstract

A voltage regulator includes a feedback regulation loop and a drive transistor configured to source current to a regulated output. A transient recovery circuit is coupled to the voltage regulator circuit and includes a first transistor coupled to source current into a control terminal of the drive transistor, wherein the source current is in addition to current sourced in response to operation of the feedback regulation loop. The first transistor is selectively actuated in response to a drop in voltage at the regulated output. The transient recovery circuit further includes a second transistor coupled to sink current from the regulated output. The sink current has a first non-zero magnitude in the quiescent operating mode of the regulator circuit. In response to an increase in voltage at the regulated output, the operation of the second transistor is modified to increase the sink current to a second, greater, non-zero magnitude.

What is claimed is: 
     
       1. A circuit, comprising:
 a voltage regulator circuit with a feedback regulation loop and a drive transistor configured to supply an output current to a regulated output node; and 
 a transient recovery circuit, comprising:
 a first transistor configured to source a first current to a control terminal of the drive transistor, wherein said first current is supplied in addition to a regulation control current applied to the control terminal of the drive transistor in response to operation of the feedback regulation loop; 
 a first control circuit configured to selectively actuate the first transistor in response to a drop in voltage at the regulated output node; 
 a second transistor configured to sink a second current from the regulated output node; and 
 a second control circuit configured to bias the second transistor to apply the second current at a first non-zero magnitude when the voltage regulator circuit is operating in a quiescent mode, sense an increase in voltage at the regulated output node and to control operation of said second transistor to increase a magnitude of the second current, from the first non-zero magnitude to a second, greater, non-zero magnitude, in response to the sensed increase in voltage at the regulated output node; 
 
 wherein the second control circuit comprises:
 a voltage copying circuit configured to copy a voltage at the regulated output node to an intermediate node in the quiescent mode; 
 a current mirror circuit including the second transistor, said current mirror circuit coupled to the regulated output node and to the intermediate node, said current mirror configured to receive an input current and output the second current; and 
 a capacitor coupled to a common control terminal of the current mirror circuit and configured to apply a fixed bias voltage to a control terminal of the second transistor. 
 
 
     
     
       2. The circuit of  claim 1 , wherein said first control circuit is configured to bias the first transistor in an off state when the voltage regulator circuit is operating in the quiescent mode, said first control circuit further configured to sense the drop in voltage at the regulated output node and respond by biasing the first transistor into an on state. 
     
     
       3. The circuit of  claim 2 , wherein the first control circuit comprises:
 a voltage copying circuit configured to copy a voltage at the regulated output node to an intermediate node in the quiescent mode; 
 a current mirror circuit coupled to the regulated output node and to the intermediate node, said current mirror configured to receive an input current and output a bias current; and 
 a resistor configured to receive the bias current and generate a bias voltage applied to a control terminal of the first transistor. 
 
     
     
       4. The circuit of  claim 3 , wherein the bias current is a fraction of the input current. 
     
     
       5. The circuit of  claim 3 , wherein the bias current has a magnitude sufficient to cause the resistor to generate the bias voltage in the quiescent mode which is less than a threshold turn on voltage of the first transistor. 
     
     
       6. The circuit of  claim 5 , wherein the current mirror circuit is configured to respond to the drop in voltage at the regulated output node and increase the bias current to a magnitude sufficient to cause the resistor to generate the bias voltage which exceeds the threshold turn on voltage of the first transistor. 
     
     
       7. The circuit of  claim 3 , wherein the input current is supplied from a regulated reference current. 
     
     
       8. The circuit of  claim 1 , wherein the second current is a fraction of the input current. 
     
     
       9. The circuit of  claim 1 , wherein the current mirror circuit is configured to respond to the increase in voltage at the regulated output node by increasing the magnitude of the second current. 
     
     
       10. The circuit of  claim 1 , wherein said transient recovery circuit further comprises:
 a third transistor configured to sink a third current from the control terminal of the drive transistor, wherein said third current is in addition to the regulation control current applied to the control terminal of the drive transistor in response to operation of the feedback regulation loop; and 
 a third control circuit configured to selectively actuate the third transistor in response to the increase in voltage at the regulated output node. 
 
     
     
       11. The circuit of  claim 10 , wherein the third control circuit is configured to convert the second current to a control signal applied to a control terminal of the third transistor. 
     
     
       12. The circuit of  claim 11 , wherein the second current at the first magnitude is insufficient to actuate the third transistor and wherein the second current at the second magnitude is sufficient to actuate the third transistor. 
     
     
       13. A circuit, comprising:
 a voltage regulator circuit with a feedback regulation loop and a drive transistor configured to supply an output current to a regulated output node; and 
 a transient recovery circuit comprising a transistor configured to be selectively actuated in response to a change in voltage at the regulated output node, said selectively actuated transistor configured to apply current to a control terminal of the drive transistor, said applied current being in addition to current applied to the control terminal of the drive transistor in response to operation of the feedback regulation loop; 
 a biasing circuit configured to bias the selectively actuated transistor, said biasing circuit comprising:
 a voltage copying circuit configured to copy a voltage at the regulated output node to an intermediate node; 
 a current mirror circuit coupled to the regulated output node and to the intermediate node, said current mirror configured to receive an input current and output a bias current; and 
 a resistor configured to receive the bias current and generate a bias voltage applied to a control terminal of the selectively actuated transistor. 
 
 
     
     
       14. The circuit of  claim 13 , wherein the biasing circuit is configured to bias the selectively actuated transistor in an off state when the voltage regulator circuit is operating in a quiescent mode, and is configured to sense the change in voltage at the regulated output node and respond by biasing the selectively actuated transistor into an on state. 
     
     
       15. The circuit of  claim 13 , wherein the current mirror circuit is configured to respond to the change in voltage at the regulated output node by increasing the bias current to a magnitude sufficient to cause the resistor to generate a bias voltage which exceeds a threshold turn on voltage of the selectively actuated transistor. 
     
     
       16. A circuit, comprising:
 a voltage regulator circuit with a feedback regulation loop and a drive transistor configured to supply an output current to a regulated output node; 
 a transient recovery circuit comprising: an additional transistor coupled to apply current to the regulated output node, said transistor configured to increase a magnitude of the applied current, from a first non-zero magnitude to a second, greater, non-zero magnitude, in response to a change in voltage at the regulated output node; and 
 a biasing circuit configured to bias the additional transistor to supply the applied current at the first non-zero magnitude when the voltage regulator circuit is operating in a quiescent mode, said biasing circuit configured to sense the change in voltage at the regulated output node and respond by increasing the magnitude of said applied current to the second non-zero magnitude; 
 wherein the biasing circuit comprises:
 a voltage copying circuit configured to copy a voltage at the regulated output node to an intermediate node in the quiescent mode; 
 a current mirror circuit including the additional transistor, said current mirror circuit coupled to the regulated output node and to the intermediate node, said current mirror configured to receive an input current and output the applied current; and 
 a capacitor coupled to a common control terminal of the current mirror circuit and configured to apply a fixed bias voltage to a control terminal of the additional transistor. 
 
 
     
     
       17. The circuit of  claim 16 , wherein the current mirror circuit is configured to respond to the change in voltage at the regulated output node by increasing the magnitude of the applied current to the second non-zero magnitude. 
     
     
       18. A circuit, comprising:
 a voltage regulator circuit with a feedback regulation loop and a drive transistor configured to supply an output current to a regulated output node; and 
 a transient recovery circuit, comprising:
 a first transistor configured to source a first current to a control terminal of the drive transistor, wherein said first current is supplied in addition to a regulation control current applied to the control terminal of the drive transistor in response to operation of the feedback regulation loop; and 
 a first control circuit configured to bias the first transistor in an off state when the voltage regulator circuit is operating in a quiescent mode, said first control circuit further configured to sense a change in voltage at the regulated output node and respond by biasing the first transistor into an on state; 
 wherein the first control circuit comprises:
 a voltage copying circuit configured to copy a voltage at the regulated output node to an intermediate node in the quiescent mode; 
 a current mirror circuit coupled to the regulated output node and to the intermediate node, said current mirror configured to receive an input current and output a bias current; and 
 a resistor configured to receive the bias current and generate a bias voltage applied to a control terminal of the first transistor. 
 
 
 
     
     
       19. The circuit of  claim 18 , wherein the bias current is a fraction of the input current. 
     
     
       20. The circuit of  claim 18 , wherein the bias current has a magnitude sufficient to cause the resistor to generate the bias voltage in the quiescent mode which is less than a threshold turn on voltage of the first transistor. 
     
     
       21. The circuit of  claim 20 , wherein the current mirror circuit is configured to respond to the drop in voltage at the regulated output node and increase the bias current to a magnitude sufficient to cause the resistor to generate the bias voltage which exceeds the threshold turn on voltage of the first transistor. 
     
     
       22. The circuit of  claim 18 , wherein the input current is supplied from a regulated reference current.