Semiconductor device having features to prevent reverse engineering

Abstract

An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.

What is claimed is: 
     
       1. An electronic circuit comprising:
 a plurality of devices having connected floating gates; and 
 a metal layer connected to the connected floating gates, 
 wherein exposing the metal layer to an ion beam results in the failure of at least one of the plurality of devices. 
 
     
     
       2. The electronic circuit of  claim 1  wherein the plurality of devices comprise active devices, the active devices consisting of N-type devices. 
     
     
       3. The electronic circuit of  claim 1  wherein the plurality of devices comprise active devices, the active devices consisting of P-type devices. 
     
     
       4. The electronic circuit of  claim 1  wherein the metal layer is a top layer.