Class-D amplifier circuits

Abstract

Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, S IN , and a first clock signal f SW . The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability whilst reducing switching power losses.

What is claimed is: 
     
       1. A Class-D amplifier circuit for amplifying an input signal comprising: an output stage comprising at least first and second switches;
 a modulator comprising a signal input for receiving said input signal and a clock input for receiving a first clock signal, the modulator being configured to control the duty cycles of said first and second switches within a switching cycle based on said input signal, wherein said switching cycle has a switching frequency based on said first clock signal; and 
 a frequency controller for controlling the frequency of said first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude; 
 wherein said modulator comprises a reference waveform generator for generating a reference waveform at a frequency based on said first clock signal; 
 wherein said reference waveform generator is configured such that the amplitude of the reference waveform is substantially the same at said first and second switching frequencies; and 
 wherein said frequency controller is configured to generate a gain control signal indicating any changes in said switching frequency and the reference waveform generator is configured to receive the gain control signal and adjust a slope of the reference waveform based on said gain control signal to compensate for any change in switching frequency. 
 
     
     
       2. A class-D amplifier circuit as claimed in  claim 1  wherein said frequency controller comprises a comparator for comparing said indication of signal amplitude to at least one threshold and wherein said frequency controller is configured to control the frequency of the clock signal based on said comparison. 
     
     
       3. A class-D amplifier circuit as claimed in  claim 2  wherein said frequency controller is configured to provide said first switching frequency if said indication of signal amplitude is above a first threshold and to provide said second switching frequency if said indication of signal amplitude is below the first threshold. 
     
     
       4. A class-D amplifier circuit as claimed in  claim 3  wherein said first threshold corresponds to a substantially quiescent input signal amplitude. 
     
     
       5. A class-D amplifier circuit as claimed in  claim 3  wherein said first threshold corresponds to a signal input amplitude which is within the range of 5-25% of the maximum signal amplitude. 
     
     
       6. A class-D amplifier circuit as claimed in  claim 2  wherein said comparator is configured to compare said indication of signal amplitude to a plurality of different thresholds, wherein each threshold corresponds to a different switching frequency. 
     
     
       7. A class-D amplifier circuit as claimed in  claim 1  wherein said indication of the amplitude of the input signal is one of:
 an envelope value for the input signal; 
 a received volume control signal; 
 derived from the output of said comparator; 
 derived from a control signal output from said modulator for controlling the switches of the output stage; or derived from an output of the output stage. 
 
     
     
       8. A class-D amplifier circuit as claimed in  claim 1  wherein said frequency controller comprises a clock generator for receiving an input clock signal and generating at least one additional clock signal from said input clock signal. 
     
     
       9. A class-D amplifier circuit for amplifying an input signal comprising:
 an output stage comprising at least first and second switches; 
 a modulator comprising a signal input for receiving said input signal and a clock input for receiving a first clock signal, the modulator being configured to control the duty cycles of said first and second switches within a switching cycle based on said input signal, wherein said switching cycle has a switching frequency based on said first clock signal; and 
 a frequency controller for controlling the frequency of said first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude; 
 wherein said frequency controller comprises a clock generator for receiving an input clock signal and generating at least one additional clock signal from said input clock signal; and 
 wherein said clock generator comprises a multiplexor configured to receive a clock signal at said first switching frequency at a first input and a clock signal at said second switching frequency at a second input and wherein the output of the multiplexer is switched between said inputs based on said indication of amplitude of the input signal. 
 
     
     
       10. A class-D amplifier circuit as claimed in  claim 9  wherein the multiplexer is controlled so that any switching of the output of the multiplexor between said inputs is timed so as to be substantially synchronized to a clock edge of both of said first and second clock signals. 
     
     
       11. A class-D amplifier as claimed in  claim 1  wherein said frequency controller is configured such that any change in switching frequency is substantially synchronized to the top or bottom of the ramp of the reference voltage waveform. 
     
     
       12. A class-D amplifier as claimed in  claim 1  wherein said reference waveform generator comprises an integrator circuit connected to at least first and second current steering branches, each current steering branch comprising at least one current source for generating a charging or discharging current based on the first clock signal wherein the second current steering branch can be enabled or disabled based on the gain control signal. 
     
     
       13. A class-D amplifier as claimed in  claim 1  wherein said reference waveform generator comprises an integrator circuit connected to at least one current steering branch, said current steering branch comprising at least one current source for generating a charging or discharging current based on the first clock signal wherein at least one current source is programmable based on the gain control signal. 
     
     
       14. A class-D amplifier as claimed in  claim 1  wherein said reference waveform generator comprises an integrator circuit comprising an op-amp and a first feedback capacitor wherein at least one additional feedback capacitor can be selectively connected in parallel with first feedback capacitor based on said gain control signal. 
     
     
       15. A class-D amplifier as claimed in  claim 1  wherein said frequency controller is configured to implement the transition from the first switching frequency to the second switching frequency or from the second switching frequency to the first switching frequency over a period of time. 
     
     
       16. A class-D amplifier circuit as claimed in  claim 15  wherein said frequency controller comprises a frequency modulator for controllably varying the first clock signal between a plurality of predetermined switching frequencies wherein said modulator controls the changing between said predetermined switching frequencies to approximate a smooth transition in switching frequency between said first and second switching frequencies. 
     
     
       17. A driver circuit comprising a class-D amplifier circuit as claimed in  claim 1  wherein said driver circuit is arranged to drive at least one of:
 an audio transducer, a haptic transducer, an ultrasound transducer; or 
 an electromechanical actuator or motor. 
 
     
     
       18. An electronic device comprising a class-D amplifier as claimed in  claim 1  wherein the device is at least one of:
 a portable device; 
 a battery powered device; 
 a mobile communications device; 
 a computing device; 
 a gaming device; 
 an audio device; or 
 an ultrasonic device. 
 
     
     
       19. A method of amplifying an input signal in a Class-D amplifier comprising:
 receiving said input signal and a first clock signal; 
 controlling the duty cycles of at least first and second switches of an output stage within a switching cycle based on said input signal and a reference waveform, where said reference waveform has a frequency based on said first clock signal; 
 receiving an indication of the amplitude of the input signal; 
 varying the frequency of said first clock signal in response to said indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude; and 
 generating a gain control signal indicating any changes in said switching frequency and adjusting a slope of the reference waveform based on said gain control signal to compensate for any change in switching frequency. 
 
     
     
       20. A Class-D amplifier circuit for amplifying an audio signal comprising:
 an output stage comprising at least first and second switches; 
 a modulator comprising a signal input for receiving said audio signal and a clock input for receiving a first clock signal, the modulator being configured to control the duty cycles of said first and second switches based on said audio signal and a cyclic reference waveform, wherein the frequency of said cyclic reference waveform depends on said first clock signal; and 
 a frequency controller for controlling the frequency of said first clock signal in response to an indication of the amplitude of the audio signal so as to provide a first frequency at a first audio signal amplitude and a second, lower, frequency at a second, lower, audio signal amplitude; 
 wherein the modulator is configured to adjust a slope of the cyclic reference waveform in accordance with changes in the frequency of the first clock signal. 
 
     
     
       21. A Class-D amplifier circuit for amplifying an audio signal comprising:
 an output stage comprising at least first and second switches; 
 a modulator comprising a signal input for receiving said audio signal and a clock input for receiving a first clock signal at a first clock frequency, the modulator being configured to generate a cyclic reference waveform at a frequency dependent on said first clock frequency and control the duty cycle, per cycle of said cyclic reference waveform, of said first and second switches based on said audio signal and said cyclic reference waveform, and 
 a frequency controller comprising a multiplexer for selectively outputting one of a plurality of input signals at different frequencies as said first clock signal in response to an indication of the amplitude of the audio signal so as to provide a first frequency at a first audio signal amplitude and a second, lower, frequency at a second, lower, audio signal amplitude.