Method of charge controlled patterning during reactive ion etching

Abstract

A method of reactive ion etching a wafer includes providing a plasma processing tool having a wafer chuck within a chamber and an electrode creating a plasma above the wafer chuck. There is provided on the wafer chuck a semiconductor wafer having a p− layer and an n+ layer. Both p− and n+ layers have exposed peripheral edges during plasma etching to electrically form with the plasma processing tool during plasma etching a diode having an anode comprising the plasma, a cathode comprising the wafer chuck and a gate comprising the n+ layer peripheral edge. The method includes controlling charge flow during plasma etching adjacent the peripheral edge of the n+ layer to reduce charge transport into, within and out of the semiconductor wafer adjacent the n+ layer edge, and reactive ion etching the n+ layer while controlling the charge flow along the edge of the n+ layer.

Thus, having described the invention, what is claimed is: 
     
       1. A method of reactive ion etching a wafer comprising:
 providing a plasma processing tool having a wafer chuck within a chamber and an electrode for creating a plasma within the chamber above the wafer chuck; 
 providing on the wafer chuck a semiconductor wafer having a p− layer and, above the p− layer, a n+ layer to be etched, the n+ layer having a peripheral edge, the p− layer having during plasma etching an exposed peripheral edge such that the semiconductor wafer electrically forms with the plasma processing tool during plasma etching an anode comprising the plasma, a cathode comprising the wafer chuck and a gate comprising the n+ layer peripheral edge; 
 controlling charge flow during plasma etching adjacent the peripheral edge of the n+ layer to reduce charge transport into, within and out of the semiconductor wafer adjacent the n+ layer peripheral edge; and 
 reactive ion etching the n+ layer while controlling the charge flow along the peripheral edge of the n+ layer. 
 
     
     
       2. The method of  claim 1  wherein charge flow during plasma etching is controlled by applying adjacent the peripheral edge of the n+ layer a coating layer of a material that reduces charge flow to the portion of the semiconductor wafer below the material, while leaving a major portion of the n+ layer surface free of the material during the reactive ion etching. 
     
     
       3. The method of  claim 2  wherein the material is an electrical non-conductor. 
     
     
       4. The method of  claim 3  wherein the material is a polymer. 
     
     
       5. The method of  claim 2  wherein the material is a resist. 
     
     
       6. The method of  claim 2  wherein the n+ layer has a bevel between the n+ layer surface and the n+ layer peripheral edge, and the coating layer extends along the n+ layer bevel. 
     
     
       7. The method of  claim 2  wherein the coating layer extends along the n+ layer peripheral edge. 
     
     
       8. The method of  claim 2  wherein the coating layer extends along a portion of the n+ layer surface adjacent the n+ layer peripheral edge. 
     
     
       9. The method of  claim 2  wherein the coating layer extends along a portion of a peripheral edge of the semiconductor wafer in contact with the wafer chuck. 
     
     
       10. The method of  claim 1  wherein charge flow during plasma etching is controlled by doping the n+ layer adjacent the n+ layer peripheral edge with an implant of an n or p type dopant that reduces charge flow to the portion of the semiconductor wafer adjacent the n+ layer peripheral edge, while leaving a major portion of the n+ layer surface free of the dopant during the reactive ion etching. 
     
     
       11. The method of  claim 1  wherein charge flow during plasma etching is controlled by providing variation in electrical conductivity between the p− layer and the wafer chuck adjacent the exposed edge of the p− layer as compared to a remaining central region of the p− layer above the wafer chuck to reduce charge flow to the portion of the semiconductor wafer adjacent the n+ layer peripheral edge. 
     
     
       12. The method of  claim 11  wherein variation in electrical conductivity between the p− layer and the wafer chuck adjacent the exposed edge of the p− layer is provided by reducing conductivity of the wafer chuck below the exposed edge of the p− layer as compared to conductivity of the wafer chuck below the remaining region of the p− layer. 
     
     
       13. The method of  claim 12  wherein variation in electrical conductivity between the p− layer and the wafer chuck adjacent the exposed edge of the p− layer is provided by reducing contact of the wafer chuck with the semiconductor wafer below the exposed edge of the p− layer as compared to contact of the wafer chuck below the remaining region of the p− layer. 
     
     
       14. The method of  claim 1  wherein charge flow during plasma etching is controlled by applying radiation selected from the group consisting of heat and electromagnetic radiation to reduce charge from adjacent the peripheral edge of the n+ layer, as compared to a remaining portion of the semiconductor wafer, during the reactive ion etching. 
     
     
       15. The method of  claim 1  wherein during reactive ion etching the plasma processing tool electrically forms a diode with the semiconductor wafer. 
     
     
       16. The method of  claim 1  wherein the reactive ion etching creates vias or trenches in the n+ layer. 
     
     
       17. A method of reactive ion etching a wafer comprising:
 providing a plasma processing tool having a wafer chuck within a chamber and an electrode for creating a plasma within the chamber above the wafer chuck; 
 providing on the wafer chuck a semiconductor wafer having a p− layer and an n+ layer, both p− and n+ layers having exposed peripheral edges during plasma etching to electrically form with the plasma processing tool during plasma etching a diode having an anode comprising the plasma, a cathode comprising the wafer chuck and a gate comprising the n+ layer peripheral edge; 
 controlling charge flow during plasma etching adjacent the peripheral edge of the n+ layer to reduce charge transport into, within and out of the semiconductor wafer adjacent the n+ layer peripheral edge; and 
 reactive ion etching the n+ layer while controlling the charge flow along the peripheral edge of the n+ layer. 
 
     
     
       18. The method of  claim 17  wherein charge flow during plasma etching is controlled by applying adjacent the peripheral edge of the n+ layer a coating layer of a material that reduces charge flow to the portion of the semiconductor wafer below the material, while leaving a major portion of the n+ layer surface free of the material during the reactive ion etching. 
     
     
       19. The method of  claim 17  wherein charge flow during plasma etching is controlled by doping the n+ layer adjacent the n+ layer peripheral edge with an implant of an n or p type dopant that reduces charge flow to the portion of the semiconductor wafer adjacent the n+ layer peripheral edge, while leaving a major portion of the n+ layer surface free of the dopant during the reactive ion etching. 
     
     
       20. The method of  claim 17  wherein charge flow during plasma etching is controlled by providing variation in electrical conductivity between the p− layer and the wafer chuck adjacent the exposed edge of the p− layer as compared to a remaining central region of the p− layer above the wafer chuck to reduce charge flow to the portion of the semiconductor wafer adjacent the n+ layer peripheral edge.