P
US9525073B2ActiveUtilityPatentIndex 63

Semiconductor device including oxide semiconductor

Assignee: SEMICONDUCTOR ENERGY LABPriority: May 30, 2014Filed: May 28, 2015Granted: Dec 20, 2016
Est. expiryMay 30, 2034(~7.9 yrs left)· nominal 20-yr term from priority
Inventors:ATSUMI TOMOAKIKOBAYASHI YOSHIYUKISHIONOIRI YUTAKAYAKUBO YUTONAGATSUKA SHUHEIYAMAZAKI SHUNPEI
G05F 3/262H10D 84/834H10D 84/82H10D 62/8503H10D 62/882H10D 30/473H10D 30/024H10D 86/441H10D 86/423H10D 86/215H10D 86/60H10D 62/405H10D 62/121H10D 62/80H10D 30/6757H10D 30/6734H10D 30/62H10D 30/014H10D 30/6755H01L 29/785H01L 29/78648H01L 29/2003H01L 27/1211H01L 27/0886H01L 29/66795H01L 27/124H01L 29/7869H01L 27/1225H01L 29/045H01L 27/085H01L 29/1606H01L 29/66439H01L 29/24H01L 29/0673H01L 29/78696H01L 29/7782
63
PatentIndex Score
2
Cited by
208
References
19
Claims

Abstract

A semiconductor device which occupies a small area is provided. A semiconductor device includes a resistor. The resistor includes a transistor. The increase rate of a drain current of the transistor with a 0.1 V change in drain voltage is preferably higher than or equal to 1% when the drain voltage is higher than a difference between a gate voltage and a threshold voltage of the transistor. The semiconductor device has a function of generating a voltage based on the resistance of the resistor.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device comprising:
 a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor each including a gate, a source, and a drain; and 
 a first wiring, a second wiring, and a third wiring, 
 wherein the gate of the first transistor is electrically connected to the first wiring, one of the source and the drain of the first transistor is electrically connected to the second wiring, and the other of the source and the drain of the first transistor is electrically connected to a first node, 
 wherein the gate of the second transistor is electrically connected to the first node, one of the source and the drain of the second transistor is electrically connected to the second wiring, and the other of the source and the drain of the second transistor is electrically connected to a second node, 
 wherein the gate of the third transistor is electrically connected to the second node, one of the source and the drain of the third transistor is electrically connected to the first node, and the other of the source and the drain of the third transistor is electrically connected to a third node, 
 wherein the gate of the fourth transistor is electrically connected to the third node, one of the source and the drain of the fourth transistor is electrically connected to the second node, and the other of the source and the drain of the fourth transistor is electrically connected to the third wiring, 
 wherein the gate of the fifth transistor is electrically connected to the third node, one of the source and the drain of the fifth transistor is electrically connected to the third node, and the other of the source and the drain of the fifth transistor is electrically connected to the third wiring, 
 wherein the first node is electrically connected to an output terminal, 
 wherein the first transistor further comprises:
 an oxide semiconductor layer electrically connected to the source and the drain of the first transistor; and 
 a gate insulating layer over the oxide semiconductor layer, the source, and the drain of the first transistor, 
 
 wherein the gate of the first transistor is positioned over the gate insulating layer and overlaps with the oxide semiconductor layer, and 
 wherein a bottom surface of the gate of the first transistor is positioned below a bottom surface of the oxide semiconductor layer. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein an increase rate of a drain current of the first transistor with a 0.1 V change in drain voltage is higher than or equal to 1% when the drain voltage is higher than a difference between a gate voltage and a threshold voltage of the first transistor. 
     
     
       3. The semiconductor device according to  claim 2 , wherein a cutoff frequency of the first transistor at a source-drain voltage higher than or equal to 1 V and lower than or equal to 2 V is higher than 2 GHz. 
     
     
       4. The semiconductor device according to  claim 1 , wherein the first transistor is capable of acting as a resistor. 
     
     
       5. The semiconductor device according to  claim 1 , wherein a channel length of the first transistor is less than or equal to 100 nm. 
     
     
       6. The semiconductor device according to  claim 1 , wherein the oxide semiconductor layer includes at least one of indium and zinc. 
     
     
       7. The semiconductor device according to  claim 1 , wherein the oxide semiconductor layer includes at least one of aluminum, gallium, yttrium, and tin. 
     
     
       8. The semiconductor device according to  claim 1 , wherein the gate of the first transistor overlaps with an upper surface of the oxide semiconductor layer and faces a side surface of the oxide semiconductor layer in a channel width direction with the gate insulating layer provided between the oxide semiconductor layer and the gate. 
     
     
       9. The semiconductor device according to  claim 1 , wherein the oxide semiconductor layer comprises a plurality of crystal parts with c-axis alignment. 
     
     
       10. A semiconductor device comprising:
 a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor each including a gate, a source, and a drain; and 
 a first wiring, a second wiring, and a third wiring, 
 wherein the gate of the first transistor is electrically connected to the first wiring, one of the source and the drain of the first transistor is electrically connected to the second wiring, and the other of the source and the drain of the first transistor is electrically connected to a first node, 
 wherein the gate of the second transistor is electrically connected to the first node, one of the source and the drain of the second transistor is electrically connected to the second wiring, and the other of the source and the drain of the second transistor is electrically connected to a second node, 
 wherein the gate of the third transistor is electrically connected to the second node, one of the source and the drain of the third transistor is electrically connected to the first node, and the other of the source and the drain of the third transistor is electrically connected to a third node, 
 wherein the gate of the fourth transistor is electrically connected to the third node, one of the source and the drain of the fourth transistor is electrically connected to the second node, and the other of the source and the drain of the fourth transistor is electrically connected to the third wiring, 
 wherein the gate of the fifth transistor is electrically connected to the third node, one of the source and the drain of the fifth transistor is electrically connected to the third node, and the other of the source and the drain of the fifth transistor is electrically connected to the third wiring, 
 wherein the first transistor further comprises:
 a first oxide semiconductor layer; 
 a second oxide semiconductor layer over the first oxide semiconductor layer, the second oxide semiconductor layer electrically connected to the source and the drain of the first transistor; 
 a third oxide semiconductor layer over the second oxide semiconductor layer, the source, and the drain of the first transistor; and 
 a gate insulating layer over the third oxide semiconductor layer, the source, and the drain of the first transistor, 
 wherein the gate of the first transistor is positioned over the gate insulating layer and overlaps with the second oxide semiconductor layer, and 
 wherein a bottom surface of the gate of the first transistor is positioned below a bottom surface of the first oxide semiconductor layer. 
 
 
     
     
       11. The semiconductor device according to  claim 10 , wherein an increase rate of a drain current of the first transistor with a 0.1 V change in drain voltage is higher than or equal to 1% when the drain voltage is higher than a difference between a gate voltage and a threshold voltage of the first transistor. 
     
     
       12. The semiconductor device according to  claim 11 , wherein a cutoff frequency of the first transistor at a source-drain voltage higher than or equal to 1 V and lower than or equal to 2 V is higher than 2 GHz. 
     
     
       13. The semiconductor device according to  claim 10 , wherein the first transistor is capable of acting as a resistor. 
     
     
       14. The semiconductor device according to  claim 10 , wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each include at least one of indium and zinc. 
     
     
       15. The semiconductor device according to  claim 10 , wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each include at least one of aluminum, gallium, yttrium, and tin. 
     
     
       16. The semiconductor device according to  claim 10 , wherein the gate of the first transistor overlaps with an upper surface of the third oxide semiconductor layer and faces a side surface of the second oxide semiconductor layer in a channel width direction with the gate insulating layer provided between the second oxide semiconductor layer and the gate. 
     
     
       17. The semiconductor device according to  claim 10 , wherein the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor layer each comprise a plurality of crystal parts with c-axis alignment. 
     
     
       18. The semiconductor device according to  claim 10 , wherein the first node is electrically connected to an output terminal. 
     
     
       19. The semiconductor device according to  claim 10 , wherein the third oxide semiconductor layer is in contact with a side surface of the second oxide semiconductor layer in a channel length direction.

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