Semiconductor memory device including a 3-dimensional memory cell array and a method of operating the same

Abstract

A semiconductor memory device may include a plurality of cell strings. Each of the cell strings may include at least one source selection transistor connected to a common source line, a plurality of memory cells connected to the common source line through the at least one source selection transistor. Each of the cell strings may include at least one source selection line connected to source selection transistors of the plurality of the cell strings. The semiconductor memory device may include peripheral circuit. The peripheral circuit may be configured to control the plurality of the cell strings. The peripheral circuit may be configured to perform a program on the source selection transistors connected to a selected source selection line by applying a program voltage to the selected source selection line among the at least one source selection line, and by applying a reference voltage to the common source line.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a plurality of cell strings, each of the plurality of the cell strings including a first source selection transistor connected to a common source line, memory cells connected to the common source line through the first source selection transistor and a drain selection transistor connected between the memory cells and a bit line; 
 a first source selection line connected to the first source selection transistors included in the plurality of the cell strings; 
 a plurality of word lines connected to the memory cells included in each of the plurality of cell strings, respectively; 
 a drain selection line connected to the drain selection transistors included in the plurality of the cell strings; and 
 a peripheral circuit configured to control the plurality of cell strings, 
 wherein the peripheral circuit is configured to perform a program on the first source selection transistors connected to the first source selection line by applying a program voltage to the first source selection line, and by applying a turn-off voltage to the drain selection line to turn-off the drain selection transistors included in the plurality of the cell strings, or floating the drain selection line. 
 
     
     
       2. The semiconductor memory device of  claim 1 ,
 wherein each of the plurality of the cell strings includes a second source selection transistor connected between the memory cells and the common source line, and 
 the peripheral circuit applies a program prohibition voltage to a second source selection line connected to the second source selection transistors included in the plurality of cell strings to prohibit the program on the second source selection transistors while the program voltage is applied to the first source selection line, and 
 wherein the program prohibition voltage is less than the program voltage. 
 
     
     
       3. The semiconductor memory device of  claim 1 ,
 wherein each of the plurality of the cell strings includes a second source selection transistor connected between the memory cells and the common source line, and 
 the peripheral circuit floats a second source selection line connected to the second source selection transistors included in the plurality of cell strings to prohibit the program on the second source selection transistors while the program voltage is applied to the first source selection line. 
 
     
     
       4. The semiconductor memory device of  claim 1 , wherein during the program, the peripheral circuit applies the reference voltage to bit lines connected to the plurality of the cell strings, the drain selection line, and the plurality of the word lines. 
     
     
       5. The semiconductor memory device of  claim 1 , wherein during the program, the peripheral circuit floats bit lines connected to the plurality of the cell strings, the drain selection line, and the plurality of the word lines. 
     
     
       6. The semiconductor memory device of  claim 1 , wherein each of the plurality of the cell strings comprises a pipe gate, the pipe gate being connected between first memory cells of the memory cells and second memory cells of the memory cells, and
 during the program, the peripheral circuit biases a pipe line connected to the pipe gate to a reference voltage or floats the pipe line connected to the pipe gate. 
 
     
     
       7. The semiconductor memory device of  claim 1 , wherein after the program, the peripheral circuit verifies whether a threshold voltage of each of the first source selection transistors connected to the first source selection line is equal to or greater than a first verification voltage. 
     
     
       8. The semiconductor memory device of  claim 7 , wherein the peripheral circuit is configured to:
 complete the program when a threshold voltage of each of the first source selection transistors is equal to or greater than the first verification voltage; and 
 program again the first source selection transistors using an increased program voltage higher than the program voltage when at least one of the first source selection transistors has a threshold voltage less than the first verification voltage. 
 
     
     
       9. The semiconductor memory device of  claim 1 , wherein first cell strings of the plurality of the cell strings are connected to first bit lines,
 second cell strings of the plurality of the cell strings are connected to second bit lines, 
 after the program, the peripheral circuit performs a first verification on the first source selection transistors included in the first cell strings, and the peripheral circuit performs a second verification on the first source selection transistors included in the second cell strings. 
 
     
     
       10. The semiconductor memory device of  claim 9 , wherein when at least one of the first verification and the second verification has failed, the peripheral circuit applies an increased program voltage higher than the program voltage to the first source selection lines to, again, program the first source selection transistors. 
     
     
       11. A method of operating a semiconductor memory device, including a plurality of cell strings, each of the plurality of cell strings including a plurality of memory cells and a plurality of source selection transistors connected between the plurality of memory cells and a common source line, the plurality of source selection transistors including a first source selection transistor and a second source selection transistor, the method comprising:
 applying a reference voltage to the common source line; 
 applying a program voltage to a first source selection line connected to the first source selection transistors included in the plurality of the cell strings to perform a program on the first source selection transistors; and 
 floating a second source selection line connected to the second source selection transistors included in the plurality of the cell strings during the applying of the program voltage to the first source selection line. 
 
     
     
       12. The method of  claim 11 , further comprising:
 after the program, 
 programming again the first source selection transistors connected to the first selected source selection line using an increased program voltage higher than the program voltage when at least one of the first source selection transistors has a threshold voltage less than a first verification voltage. 
 
     
     
       13. The method of  claim 11 ,
 wherein each of the plurality of the cell strings includes a drain selection transistor connected between the plurality of memory cells and a bit line, and 
 during the applying of the program voltage to the first source selection line, a turn-off voltage is applied to a drain selection line to turn off the drain selection transistors connected to the drain selection line and included in the plurality of the cell strings, or the drain selection line is floated. 
 
     
     
       14. The method of  claim 13 ,
 wherein each of the plurality of the cell strings comprises a pipe gate, the pipe gate being connected between first memory cells of the plurality of memory cells and second memory cells of the plurality of memory cells, and 
 a pipe line connected to the pipe gates included in the plurality of the cell strings is biased to a reference voltage or floated during the applying of the program voltage to the first source selection line. 
 
     
     
       15. A semiconductor memory device including a 3-dimensional memory cell array structure, the semiconductor memory device comprising:
 a cell string including:
 a plurality of memory cells; 
 a first source selection transistor connected between the plurality of memory cells and a common source line; and 
 a plurality of word lines connected to the plurality of memory cells respectively; 
 
 a first source selection line connected to a gate of the first source selection transistor included in the cell string; and 
 a peripheral circuit connected to the plurality of word lines, the common source line and the first source selection line, 
 wherein the peripheral circuit is configured to perform a program on the first source selection transistor by applying a program voltage to the first source selection line, by applying a reference voltage to the common source line, and by applying a plurality of voltages to the plurality of word lines to turn-off at least one of the plurality of memory cells or floating at least one of the plurality of word lines. 
 
     
     
       16. The semiconductor memory device of  claim 15 , wherein the cell string further includes a second source selection transistor connected between the plurality of memory cells and the common source line and connected to a second source selection line, and
 the second source selection line is floated while the program voltage is applied to the first source selection line. 
 
     
     
       17. The semiconductor memory device of  claim 15 , wherein the cell string further includes a drain selection transistor connected between a bit line and the plurality of memory cells, and
 a ground voltage is applied to a drain selection line connected to the drain selection transistor while the program voltage is applied to the first source selection line. 
 
     
     
       18. The semiconductor memory device of  claim 15 , wherein after the program, the peripheral circuit verifies whether a threshold voltage of each of the first source selection transistors connected to the first source selection line is equal to or greater than a first verification voltage. 
     
     
       19. The semiconductor memory device of  claim 18 , wherein the peripheral circuit is configured to program again the first source selection transistors using an increased program voltage higher than the program voltage when at least one of the first source selection transistors has a threshold voltage less than the first verification voltage. 
     
     
       20. The semiconductor memory device of  claim 15 , wherein each of the plurality of the cell strings comprises a pipe gate, the pipe gate being connected between first memory cells among the plurality of memory cells and second memory cells among the plurality of memory cells, and
 while the program voltage is applied to the first source selection line, the peripheral circuit biases a pipe line connected to the pipe gate to a reference voltage or floats the pipe line connected to the pipe gate.