Electronic device package, electronic device structure and method of fabricating electronic device package

Abstract

According to embodiments of the disclosure, an electronic device package may include a wire layer and a rigid element. The wire layer includes a first surface and a second surface opposite to each other, and the second surface of the wire layer has at least one coarse structure. A portion of the second surface having the coarse structure has a greater roughness than another portion of the second surface. The rigid element is disposed on the first surface of the wire layer, wherein a stiffness of the rigid element is greater than a stiffness of the wire layer and a projection area of the coarse structure on the first surface of the wire layer overlaps an edge of the rigid element.

What is claimed is: 
     
       1. An electronic device package, comprising:
 a wire layer comprising a first surface and a second surface opposite to each other, and the second surface of the wire layer having at least one coarse structure, wherein a portion of the second surface having the coarse structure has a greater roughness than another portion of the second surface; 
 a rigid element disposed on the first surface of the wire layer, wherein a stiffness of the rigid element is greater than a stiffness of the wire layer; 
 a projection area of one of the at least one coarse structure on the first surface of the wire layer overlaps an edge of the rigid element; and 
 a molding layer disposed on the first surface of the wire layer to encapsulate the rigid element. 
 
     
     
       2. The electronic device package of  claim 1 , wherein the wire layer comprises a dielectric matrix and a plurality of wirings distributed in the dielectric matrix, and the rigid element is electrically connected to the wirings. 
     
     
       3. The electronic device package of  claim 2 , wherein the coarse structure is formed on the dielectric matrix. 
     
     
       4. The electronic device package of  claim 2 , wherein at least one of the wirings comprises a fan-out portion and a conductive via, the fan-out portion is disposed on the first surface to be electrically connected to the rigid element, and the conductive via is connected to the fan-out portion and passes through the dielectric matrix. 
     
     
       5. The electronic device package of  claim 4 , further comprising at least one conductive bump disposed on the second surface of the wire layer and electrically connected to the conductive via. 
     
     
       6. The electronic device package of  claim 5 , further comprising a passivation structure disposed on the second surface of the wire layer, wherein the passivation structure has at least one opening and the conductive bump is located at the opening. 
     
     
       7. The electronic device package of  claim 1 , wherein the at least one coarse structure is a plural in quantity, the projection area of another of the coarse structure on the first surface of the wire layer overlaps with another part of the projection area of the rigid element on the first surface of the wire layer at a middle portion of the rigid element. 
     
     
       8. The electronic device package of  claim 1 , wherein the projection area of the one of the at least one coarse structure overlaps with a whole of a projection area of the rigid element on the first surface of the wire layer. 
     
     
       9. The electronic device structure of  claim 1 , wherein the wire layer further comprising at least one through hole passing through the wire layer and the molding layer. 
     
     
       10. An electronic device structure, comprising:
 a carrier; 
 a wire layer, disposed on the carrier, wherein the wire layer has a first surface and a second surface opposite to each other, the second surface has at least one coarse structure, and a portion of the second surface having the coarse structure has a greater roughness than another portion of the second surface; 
 a plurality of rigid elements disposed on the wire layer, wherein each of the rigid elements is disposed on the first surface, a stiffness of the each of the rigid elements is greater than a stiffness of the wire layer, and a projection area of the coarse structure on the first surface of the wire layer overlaps an edge of the each of the rigid elements; and 
 a releasing layer disposed between the carrier and the wire layer. 
 
     
     
       11. The electronic device structure of  claim 10 , wherein the wire layer comprises a dielectric matrix and a plurality of wiring units distributed in the dielectric matrix, and the rigid elements are electrically connected to the wiring units respectively. 
     
     
       12. The electronic device structure of  claim 11 , wherein each of the wiring units comprises a plurality of wirings, at least one of the wirings comprises a fan-out portion and a conductive via, the fan-out portion is disposed on the first surface to be electrically connected to the rigid element, and the conductive via is connected to the fan-out portion and passes through the dielectric matrix. 
     
     
       13. The electronic device structure of  claim 11 , wherein the coarse structure is formed on the dielectric matrix. 
     
     
       14. The electronic device structure of  claim 10 , further comprising a molding layer disposed on the first surface of the wire layer to encapsulate the rigid elements. 
     
     
       15. The electronic device structure of  claim 10 , wherein the at least one coarse structure is a plural in quantity, the projection area of another of the coarse structures on the first surface of the wire layer overlaps with another part of the projection area of the each of the rigid elements on the first surface of the wire layer at a middle portion. 
     
     
       16. The electronic device structure of  claim 10 , wherein the projection area of the at least one coarse structure overlaps with a whole of a projection area of a corresponding rigid element on the first surface of the wire layer. 
     
     
       17. The electronic device structure of  claim 10 , wherein the rigid elements are a plurality of chips or dies, and a material of the carrier is glass. 
     
     
       18. The electronic device structure of  claim 10 , wherein a releasing force of the releasing layer with respect to the wire layer is less than or equal to 30 gf/cm. 
     
     
       19. The electronic device structure of  claim 10 , wherein the wire layer further comprising at least one through hole passing through the wire layer and the molding layer. 
     
     
       20. A method of fabricating an electronic device package, comprising:
 temporarily disposing a wire layer on a carrier with a release layer being located between the carrier and the wire layer, wherein the wire layer has a first surface and a second surface, and the second surface is in contact with the release layer; 
 forming at least one rigid element on the first surface of the wire layer to form a first area and a second area, and a stiffness of a portion of the first area is greater than a stiffness of the second area; and 
 irradiating a laser beam from the carrier toward the release layer located in the first area, wherein a predetermined path of the laser beam falls in the first area. 
 
     
     
       21. The method of  claim 20 , further removing the carrier from the wire layer through the releasing layer in a direction that an edge of the rigid element subjected to a separating force earlier than the other portion of the rigid element, wherein the predetermined path overlaps with the edge. 
     
     
       22. The method of  claim 20 , wherein the predetermined path overlaps with the rigid element at an edge. 
     
     
       23. The method of  claim 20 , wherein the predetermined path overlaps with the rigid elements at an edge and an opposite edge. 
     
     
       24. The method of  claim 20 , wherein the predetermined path overlaps with the rigid elements at an edge, an opposite edge and a middle portion between the edge and the opposite edge.