Inverter control circuit and inverter circuit

Abstract

An inverter control circuit has a quantizer configured to generate a switching signal which changes over switches of a main circuit converting a DC voltage into an AC voltage, and a filter circuit configured to generate a signal having specific transfer characteristic by using a signal correlated with an output voltage of an LC filter which smooths the AC voltage and an instruction signal corresponding to a target value of an output voltage of the main circuit, wherein the quantizer generates the switching signal by quantizing an output signal of the filter circuit.

The invention claimed is: 
     
       1. An inverter control circuit comprising:
 a quantizer to generate a switching signal which changes over switches of a main circuit converting a DC voltage into an AC voltage; 
 a filter circuit to generate a signal having specific transfer characteristic based on a signal correlated with an output voltage of an LC filter which smoothes the AC voltage and an instruction signal corresponding to a target value of an output voltage of the main circuit so that the signal correlated with the output voltage of the LC filter follows the instruction signal; 
 an A/D converter to convert the output voltage of the LC filter into a digital signal, 
 wherein the quantizer generates the switching signal by quantizing an output signal of the filter circuit; 
 
       wherein a signal input to the filter circuit, which is correlated with the output voltage of the LC filter, is the digital signal; and
 wherein the A/D converter and the filter circuit operate in synchronism with a first clock signal, and the quantizer operates in synchronism with a second clock signal having a frequency equal to or lower than a frequency of the first clock signal. 
 
     
     
       2. The circuit of  claim 1  further comprising a clock frequency adjuster to adjust the frequency of the second clock signal based on a result of counting the number of times of change in logic of an output signal of the quantizer. 
     
     
       3. The circuit of  claim 2 , wherein the clock frequency adjuster generates the second clock signal by dividing the first clock signal. 
     
     
       4. The circuit of  claim 1  further comprising a clock frequency adjuster to adjust the frequency of the second clock signal based on an amplitude value of the instruction signal.