Scan flip-flop circuit with dedicated clocks

Abstract

In one form, a scan flip-flop includes a clock gating cell and a dedicated clock flip-flop. The clock gating cell provides an input clock input signal as a scan clock signal when a scan shift enable signal is active, and provides the input clock signal as a data clock signal when the scan shift enable signal is inactive. The dedicated clock flip-flop stores a data input signal and provides the data input signal, so stored, as a data output signal in response to transitions of the data clock signal, and stores a scan data input signal and provides the scan data input signal, so stored, as the data output signal in response to transitions of the scan clock signal. The clock gating cell may further provide the input clock signal as the data clock signal when both a scan shift enable signal is inactive and a data enable signal is active.

What is claimed is: 
     
       1. A scan flip-flop circuit comprising:
 a clock gating cell for providing an input clock signal as a scan clock signal when a scan enable signal is active, and for providing said input clock signal as a data clock signal when said scan enable signal is inactive; and 
 a dedicated clock flip-flop for storing a data input signal and providing said data input signal, so stored, as a data output signal in response to transitions of said data clock signal, and for storing a scan data input signal and providing said scan data input signal, so stored, as said data output signal in response to transitions of said scan clock signal. 
 
     
     
       2. The scan flip-flop circuit of  claim 1  wherein:
 said clock gating cell further provides said input clock signal as said data clock signal when both said scan enable signal is inactive and a data enable signal is active. 
 
     
     
       3. The scan flip-flop circuit of  claim 2  wherein said clock gating cell comprises:
 a first AND gate having a first input for receiving said scan enable signal, a second input for receiving said input clock signal, and an output for providing said scan clock signal; 
 a second AND gate having a first input for receiving said input clock signal, a second input, and an output for providing said data clock signal; 
 a third AND gate having a first inverting input for receiving said scan enable signal, a second input for receiving said data enable signal, and an output; and 
 a latch having a data input coupled to said output of said third AND gate, a clock input for receiving said input clock signal, and an output coupled to said second input of said second AND gate. 
 
     
     
       4. The scan flip-flop circuit of  claim 1  wherein said dedicated clock flip-flop comprises a sense amplifier flip flop. 
     
     
       5. The scan flip-flop circuit of  claim 1  wherein said dedicated clock flip-flop comprises an asymmetric precharged flip-flop. 
     
     
       6. The scan flip-flop circuit of  claim 5  wherein said asymmetric precharged flip-flop includes an integral logic function. 
     
     
       7. The scan flip-flop circuit of  claim 1  wherein said dedicated clock flip-flop comprises a master-slave flip-flop. 
     
     
       8. The scan flip-flop circuit of  claim 7  wherein said master-slave flip-flop comprises:
 an input multiplexer for providing said scan data signal to a first node in response to an activation of said scan clock signal, and for providing said scan data signal to said first node in response to an activation of said data clock signal; 
 a master latch coupled to said first node, for latching a voltage on said first node in response to a first latch clock signal; 
 a clocked gate for transferring a logic state on said first node to a second node in response to a second latch clock signal; 
 a slave latch coupled to said second node, for latching a voltage on said second in response to said second latch clock signal; and 
 an output buffer having an input coupled to said second node, and an output for providing an output of said master-slave flip-flop. 
 
     
     
       9. The scan flip-flop circuit of  claim 8  wherein said master-slave flip-flop further comprises:
 a local clock gating cell for providing said first latch clock in response to both said scan clock and said data clock being in a first logic state, and for providing said second latch clock in response to both said scan clock signal and said data clock signal being in a second logic state. 
 
     
     
       10. The scan flip-flop circuit of  claim 8  wherein said input multiplexer comprises:
 a first transistor having a first current electrode coupled to a power supply voltage terminal, a control electrode for receiving a complement of said scan clock signal, and a second current electrode; 
 a second transistor having a first current electrode coupled to said second current electrode of said first transistor, a control electrode for receiving said scan data signal, and a second current electrode coupled to said first node; 
 a third transistor having a first current electrode coupled to said first node, a control electrode for receiving said scan data signal, and a second current electrode; 
 a fourth transistor having a first current electrode coupled to said second current electrode of said third transistor, a control electrode for receiving said scan clock signal, and a second current electrode coupled to a second power supply voltage terminal; 
 a fifth transistor having a first current electrode coupled to said power supply voltage terminal, a control electrode for receiving a complement of said data clock signal, and a second current electrode; 
 a sixth transistor having a first current electrode coupled to said second current electrode of said fifth transistor, a control electrode for receiving said data signal, and a second current electrode coupled to said first node; 
 a seventh transistor having a first current electrode coupled to said first node, a control electrode for receiving said data signal, and a second current electrode; and 
 an eighth transistor having a first current electrode coupled to said second current electrode of said seventh transistor, a control electrode for receiving said data clock signal, and a second current electrode coupled to said second power supply voltage terminal. 
 
     
     
       11. A microprocessor comprising:
 a first functional circuit having an output; 
 a second functional circuit having an input; 
 a scan chain disposed between said output of said first functional circuit and said input of said second functional circuit, wherein said scan chain captures said output of said first functional circuit and provides said output, so captured, to said input of said second functional circuit in a functional mode, and scans scan data into said scan chain and provides said scan data, so scanned, to said input of said second functional circuit in a scan mode, 
 wherein said scan chain comprises:
 a clock gating cell for providing an input clock signal as a scan clock signal when a scan enable signal is active, and for providing said input clock signal as a data clock signal when said scan enable signal is inactive; and 
 a dedicated clock flip-flop for storing a data input signal and providing said data input signal, so stored, as a data output signal in response to transitions of said data clock signal, and for storing a scan data input signal and providing said scan data input signal, so stored, as said data output signal in response to transitions of said scan clock signal. 
 
 
     
     
       12. The microprocessor of  claim 11 , wherein the microprocessor is a pipelined microprocessor and said first and second functional circuits correspond to first and second pipeline stages of the microprocessor, respectively. 
     
     
       13. The microprocessor of  claim 11 , wherein said scan chain further comprises:
 a plurality of flip-flops including said dedicated clock flip-flop and a plurality of additional dedicated clock flip-flops coupled in series. 
 
     
     
       14. The microprocessor of  claim 13 , further comprising:
 a test access port controller for providing said scan data input signal said dedicated clock flip-flop during said scan mode. 
 
     
     
       15. The microprocessor of  claim 13 , further comprising:
 a second clock gating cell coupled to at least some of said plurality of additional dedicated clock flip-flops. 
 
     
     
       16. A method comprising:
 receiving an input clock signal and a scan enable signal; 
 generating a scan clock signal from said input clock signal when said scan enable signal is active; 
 generating a data clock signal from said input clock signal when said scan enable signal is inactive; 
 storing a data input signal and providing said data input signal, so stored, as a data output signal in response to transitions of said data clock signal; and 
 storing a scan data input signal and providing said scan data input signal, so stored, as said data output signal in response to transitions of said scan clock signal. 
 
     
     
       17. The method of  claim 16  further comprising performing said storing said data input signal and said storing said scan data input signal using sense amplifier flip-flop. 
     
     
       18. The method of  claim 16  further comprising performing said storing said data input signal and said storing said scan data input signal using an asymmetric precharged flip-flop. 
     
     
       19. The method of  claim 18  wherein said performing said storing said data input signal and said storing said scan data input signal using said asymmetric precharged flip-flop comprises performing an integral logic function. 
     
     
       20. The method of  claim 16  further comprising performing said storing said data input signal and said storing said scan data input signal using a master-slave flip-flop.