Methods and apparatus for true high dynamic range imaging

Abstract

When imaging bright objects, a conventional detector array can saturate, making it difficult to produce an image with a dynamic range that equals the scene's dynamic range. Conversely, a digital focal plane array (DFPA) with one or more m-bit counters can produce an image whose dynamic range is greater than the native dynamic range. In one example, the DFPA acquires a first image over a relatively brief integration period at a relatively low gain setting. The DFPA then acquires a second image over longer integration period and/or a higher gain setting. During this second integration period, counters may roll over, possibly several times, to capture a residue modulus 2 m of the number of counts (as opposed to the actual number of counts). A processor in or coupled to the DFPA generates a high-dynamic range image based on the first image and the residues modulus 2 m .

The invention claimed is: 
     
       1. A method of generating a digital representation of a scene with a detector element operably coupled to an m-bit counter, the method comprising:
 generating, in the m-bit counter, a first count representative of detections by the detector element during a first integration period; 
 generating, in the m-bit counter, a second count representative of detections by the detector element during a second integration period; 
 concatenating k bits of the first count with at least l bits of the second count to form a third count; and 
 forming the digital representation based at least in part on the third count, the digital representation having a dynamic range greater than a dynamic range of the m-bit counter, 
 wherein m, k, and l are positive integers, k≦m, l≦m, and l+k≧m+1. 
 
     
     
       2. The method of  claim 1 , wherein generating the second count comprises counting more than 2 m −1 detections by the detector element during the second integration period. 
     
     
       3. The method of  claim 2 , wherein concatenating the k bits of the first count with the at least l bits of the second count comprises appending the at least l bits of the second count to the most significant bits of the first count. 
     
     
       4. The method of  claim 3 , wherein k<m and l=m. 
     
     
       5. The method of  claim 3 , wherein k=m and l<m. 
     
     
       6. The method of  claim 1 , further comprising:
 setting a gain of the detector element to be greater during the second integration period than during the first integration period. 
 
     
     
       7. The method of  claim 1 , further comprising:
 selecting the second integration period to be 2 k+l−m  times longer than the first integration period. 
 
     
     
       8. The method of  claim 1 , further comprising:
 removing p most significant bits of the first count and p least significant bits of the second count prior to concatenating the k bits of the first count with the at least l bits of the second count, 
 wherein p is a positive integer less than m. 
 
     
     
       9. The method of  claim 1 , further comprising:
 performing a comparison of m−k least significant bits of the first count to m−k most significant bits of the second count; and 
 concatenating the k bits of the first count with the at least l bits of the second count based on the comparison. 
 
     
     
       10. The method of  claim 9 , wherein performing the comparison comprises determining if a difference between the m−k least significant bits of the first count to the m−k most significant bits of the second count is greater than or equal to a predetermined value. 
     
     
       11. A system for generating a digital representation of a scene, the system comprising:
 a detector element to detect incident photons during a first integration period and during a second integration period; 
 an m-bit counter, operably coupled to the detector element, to generate a first count of representative of photons detected by the detector element during the first integration period and a second count representative of photons detected by the detector element during the second integration period; and 
 a processor, operably coupled to the m-bit counter, to concatenate k bits of the first count with at least l bits of the second count to form a third count and to generate the digital representation based at least in part on the third count, the digital representation having a dynamic range greater than a dynamic range of the m-bit counter, 
 wherein m, k, and l are positive integers, k≦m, l≦m, and l+k≧m+1. 
 
     
     
       12. The system of  claim 11 , wherein the detector element has a gain configured to be greater during the second integration period than during the first integration period. 
     
     
       13. The system of  claim 11 , wherein the m-bit counter is configured to generate the second count by counting more than 2 m −1 detections by the detector element during the second integration period. 
     
     
       14. The system of  claim 13 , wherein the processor is configured to concatenate the k bits of the first count with the at least l bits of the second count by appending the at least l bits of the second count to the most significant bits of the first count. 
     
     
       15. The system of  claim 14 , wherein k<m and l=m. 
     
     
       16. The system of  claim 14 , wherein k=m and l<m. 
     
     
       17. The system of  claim 11 , wherein the second integration period is 2 k+l−m  times longer than the first integration period. 
     
     
       18. The system of  claim 11 , wherein the processor is configured to remove p most significant bits of the first count and p least significant bits of the second count prior to concatenating the k bits of the first count with the at least l bits of the second count, and
 wherein p is a positive integer less than m. 
 
     
     
       19. The system of  claim 11 , wherein the processor is configured to perform a comparison of m−k least significant bits of the first count to m−k most significant bits of the second count and to concatenate the k bits of the first count with the at least l bits of the second count based on the comparison. 
     
     
       20. The system of  claim 19 , wherein the processor is configured to perform the comparison by determining if a difference between the m−k least significant bits of the first count to the m−k most significant bits of the second count is greater than or equal to a predetermined value.