US9620419B2ActiveUtilityA1

Elongated contacts using litho-freeze-litho-etch process

81
Assignee: TEXAS INSTRUMENTS INCPriority: Dec 17, 2013Filed: Mar 3, 2016Granted: Apr 11, 2017
Est. expiryDec 17, 2033(~7.4 yrs left)· nominal 20-yr term from priority
H10P 76/204H10P 76/2041H10P 50/283H10P 50/73H10W 20/0698H10W 20/089H10W 20/081H10W 20/076H10W 20/057H10W 20/056H10W 20/43H10W 20/033H10W 10/011H10W 10/10H01L 21/0273H01L 21/76843H01L 21/76802H01L 21/76879H01L 27/0207H01L 21/76816H01L 21/31144H01L 21/76877H01L 21/823871H01L 21/0274H01L 21/76831H01L 21/76895H01L 21/762H01L 21/823475H10D 89/10H10D 84/0186H10D 84/0149H10D 84/038
81
PatentIndex Score
2
Cited by
7
References
8
Claims

Abstract

A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a contact etch mask. A process of forming an integrated circuit containing elongated contacts which connect to three active areas and/or MOS gates, and elongated contacts which connect to two active areas and/or MOS gates and directly connect to a first level interconnect, using a litho-freeze-litho-etch process for a first level interconnect trench etch mask. A process of forming the integrated circuit using a litho-freeze-litho-etch process for a contact etch mask and a litho-freeze-litho-etch process for a first level interconnect trench etch mask.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A method of forming an integrated circuit, comprising the steps:
 forming a pre metal dielectric (PMD) layer over active areas and transistor gates of the integrated circuit; 
 forming a contact etch mask over the PMD layer, by a process including the steps:
 forming a first photoresist layer over the PMD layer; 
 performing a first exposure operation on the first photoresist layer with a first contact subpattern; 
 developing the first photoresist layer; 
 performing a freeze process on the first photoresist layer to form a first contact etch submask of the contact etch mask; 
 forming a second photoresist layer over the PMD layer; 
 performing a second exposure operation on the second photoresist layer with a second contact subpattern; 
 developing the second photoresist layer to form a second contact etch submask of the contact etch mask, so that contact areas are exposed by the combined first contact etch submask and second contact etch submask of the contact etch mask; 
 
 etching contact holes in the PMD layer in the contact areas defined by the contact etch mask; 
 filling the contact holes with metal to form contacts, the contacts including:
 dual node elongated contacts which connect to exactly two areas selected from the active areas and the transistor gates; and 
 multiple node elongated contacts which connect to three or more areas selected from the active areas and transistor gates; 
 
 forming an intra metal dielectric (IMD) layer above the PMD layer; 
 etching interconnect trenches in the IMD layer; 
 filling the interconnect trenches with interconnect metal to form first level interconnects, so that each of the dual node elongated contacts is directly connected to at least one of the first level interconnects. 
 
     
     
       2. The method of  claim 1 , further including the steps:
 forming a contact hard mask layer over the PMD layer prior to forming the contact etch mask; and 
 performing a contact hard mask etch process on the integrated circuit after forming the contact etch mask and prior to the step of etching the plurality of the contact holes in the PMD layer, so as to remove material from the contact hard mask layer in the contact areas to form contact hard mask holes, so that the step of etching the plurality of the contact holes in the PMD layer is performed using the contact hard mask layer as a template. 
 
     
     
       3. The method of  claim 1 , wherein the step of filling the contact holes with metal includes:
 forming a contact liner metal in the contact holes; and 
 forming a contact fill metal in the contact holes. 
 
     
     
       4. The method of  claim 1 , wherein the step of filling the interconnect trenches with interconnect metal includes:
 forming a trench liner metal in the interconnect trenches; and 
 forming a trench fill metal in the interconnect trenches. 
 
     
     
       5. A method of forming an integrated circuit, comprising the steps:
 forming a pre metal dielectric (PMD) layer over active areas and transistor gates of the integrated circuit; 
 forming a contact etch mask over the PMD layer, by a process including the steps:
 depositing, exposing, and developing a first photoresist layer to form a first submask of the contact etch mask over the PMD layer; 
 performing a freeze process on the first submask of the contact etch mask; 
 after performing the freeze process, depositing, exposing and developing a second photoresist layer to form a second submask of the contact etch mask over the PMD layer, wherein contact areas are exposed by the combined first submask and second submask of the contact etch mask; 
 
 etching contact holes in the PMD layer in the contact areas defined by the contact etch mask; 
 filling the contact holes with metal to form contacts, the contacts including:
 dual node elongated contacts which connect to exactly two areas selected from the active areas and the transistor gates; and 
 multiple node elongated contacts which connect to three or more areas selected from the active areas and transistor gates; 
 
 forming an intra metal dielectric (IMD) layer above the PMD layer; 
 etching interconnect trenches in the IMD layer; 
 filling the interconnect trenches with interconnect metal to form first level interconnects, wherein each of the dual node elongated contacts is directly connected to at least one of the first level interconnects. 
 
     
     
       6. The method of  claim 5 , further including the steps:
 forming a contact hard mask layer over the PMD layer prior to forming the contact etch mask; and 
 performing a contact hard mask etch process on the integrated circuit after forming the contact etch mask and prior to the step of etching the plurality of the contact holes in the PMD layer, so as to remove material from the contact hard mask layer in the contact areas to form contact hard mask holes, so that the step of etching the plurality of the contact holes in the PMD layer is performed using the contact hard mask layer as a template. 
 
     
     
       7. The method of  claim 6 , wherein the step of filling the contact holes with metal includes:
 forming a contact liner metal in the contact holes; and 
 forming a contact fill metal in the contact holes. 
 
     
     
       8. The method of  claim 7 , wherein the step of filling the interconnect trenches with interconnect metal includes:
 forming a trench liner metal in the interconnect trenches; and 
 forming a trench fill metal in the interconnect trenches.

Cited by (0)

No later patents cite this yet.

References (0)

No backward citations on record.