High speed switching

Abstract

Switching circuits are implemented in a manner that facilitates fast switching, which can be effected while also maintaining relatively low power dissipation. As may be implemented in connection with one or more embodiments, an apparatus includes a transistor connected between an input port and an output port, and a gate that switches between on and off states. A charge storage circuit stores a charge, and a switching circuit operates by switching the transistor between the on and off states as follows. In a first charging mode, a voltage is coupled across the charge storage circuit and a charge is stored therein, while decoupling the transistor from the charge storage circuit. In a second discharge mode, the transistor is switched from the off state to the on state, while coupling the stored charge across the gate and one of the source and drain of the transistor.

What is claimed is: 
     
       1. An apparatus comprising:
 an input port connected to a source of data signals; 
 an output port connected to a receiver for the data signals; 
 a transistor having a source and drain connected in series between the input port and the output port, and a gate configured and arranged to switch the transistor between an on state in which the transistor is configured to transfer data signals received on the input port to the output port by connecting the input port to the output port, and an off state in which the transistor disconnects the input port from the output port; 
 a charge storage circuit configured and arranged to store a charge; and 
 a switching circuit configured and arranged to switch the transistor between the on state and the off state by
 in a first mode, coupling a voltage across the charge storage circuit and storing a charge in the charge storage circuit while decoupling the transistor from the charge storage circuit, and 
 in a second mode, switching the transistor from the off state to the on state by coupling the stored charge across the gate and one of the source and drain of the transistor. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein the switching circuit is configured and arranged to:
 operate in the first mode by disconnecting the transistor from the charge storage circuit and thereafter connecting the charge storage circuit between a voltage supply port and a ground-level port; and 
 operate in the second mode by disconnecting the charge storage circuit from the voltage supply port and the ground-level port and thereafter connecting the charge storage circuit across the gate and source or drain. 
 
     
     
       3. The apparatus of  claim 1 , wherein decoupling the transistor from the charge storage circuit includes maintaining switches between the charge storage circuit and the transistor in an open state. 
     
     
       4. The apparatus of  claim 1 , wherein the charge storage circuit is configured and arranged with the transistor to, in the second mode, apply a gate-source or gate-drain voltage of the transistor that is about constant, upon coupling of the stored charge across the gate and source or drain, therein mitigating delays in a start of data flow through the source and drain of the transistor upon switching of the transistor from the off state to the on state. 
     
     
       5. The apparatus of  claim 1 , wherein
 the switching circuit is configured and arranged to, in the first mode, couple the voltage across the charge storage circuit by coupling the charge storage circuit to a power supply having a power supply voltage, and 
 the charge storage circuit is configured and arranged with the transistor to, in the second mode, set the gate-source or gate-drain voltage of the transistor to the power supply voltage, therein mitigating delays in a start of data flow through the source and drain of the transistor upon switching of the transistor from the off state to the on state. 
 
     
     
       6. The apparatus of  claim 1 , wherein the switching circuit is configured and arranged with the transistor to, in the second mode, use the stored charge to bias the gate to the stored charge level while coupling a bias voltage supply node to the gate, by biasing the gate with the stored charge while the bias voltage applied to the gate ramps from a low voltage level to the bias voltage level, wherein a time delay in ramping up the bias voltage at the gate to the bias voltage level is mitigated via the stored charge. 
     
     
       7. The apparatus of  claim 1 , wherein the switching circuit is configured and arranged to switch between the first mode and the second mode by
 decoupling the transistor from a supply voltage that is used to couple the voltage across the charge storage circuit, 
 operating in a delay mode for a delay time period during which the charge storage circuit is decoupled from both the supply voltage and the transistor, and 
 after the delay mode operate in the second mode by coupling the charge storage circuit across the gate and the one of the source and drain of the transistor while maintaining the decoupling of the transistor from the supply voltage. 
 
     
     
       8. An apparatus comprising:
 a transistor having a source and drain connected in series between an input port and an output port, and a gate configured and arranged to switch the transistor between an on state in which the transistor connects the input port to the output port, and an off state in which the transistor disconnects the input port from the output port; 
 a charge storage circuit configured and arranged to store a charge; and 
 a switching circuit configured and arranged to switch the transistor between the on state and the off state by
 in a first mode, coupling a voltage across the charge storage circuit and storing a charge in the charge storage circuit while decoupling the transistor from the charge storage circuit, and 
 in a second mode, switching the transistor from the off state to the on state by coupling the stored charge across the gate and one of the source and drain of the transistor; 
 
 wherein the charge storage circuit includes a capacitor having first and second capacitor plates, and wherein the switching circuit includes:
 a first set of switches configured and arranged to connect the first capacitor plate to an input voltage supply port and to connect the second capacitor plate to a ground-level port, 
 a second set of switches configured and arranged to connect the first capacitor plate to the gate and to connect the second capacitor plate to the one of the source and the drain of the transistor across which the stored charged is coupled, and 
 a control circuit configured and arranged to:
 in the first mode, couple the first capacitor plate to the input voltage supply port and couple the second capacitor plate to the ground-level port by operating the first set of switches in a closed state and operating the second set of switches in an open state, and 
 in the second mode, couple the first capacitor plate to the gate and couple the second capacitor plate to the source or drain by operating the first set of switches in an open state and operating the second set of switches in a closed state, therein mitigating delays in a start of data flow through the source and drain of the transistor upon switching the transistor from the off state to the on state. 
 
 
 
     
     
       9. The apparatus of  claim 8 , wherein the control circuit is configured and arranged with the first and second set of switches to ensure non-overlapping operation of the first and second sets of switches in which the first set of switches is opened before the second set of switches is closed. 
     
     
       10. The apparatus of  claim 8 , wherein the switches include a cross-coupled NAND gate and inverters configured and arranged to be triggered by a one-shot signal that initiates operation of the respective first and second modes. 
     
     
       11. An apparatus comprising:
 a first circuit configured and arranged to store a charge; 
 a transistor having a source, drain and gate, the transistor being configured and arranged to operate in an on state in which data received on an input port is passed between the input port and an output port via the source and drain, and in an off state in which data received on the input port is not passed between the input port and the output port; and 
 a second circuit configured and arranged to
 operate in a first mode by coupling a supply voltage to the first circuit and storing the charge in the first circuit, and 
 operate in a second mode by decoupling the supply voltage from the first circuit and, after decoupling the supply voltage from the first circuit, coupling the stored charge across the gate and one of the source and drain of the transistor. 
 
 
     
     
       12. The apparatus of  claim 11 , wherein the second circuit is configured and arranged to use the stored charge to raise the gate-source or the gate-drain voltage of the transistor toward the level of the stored charge while the supply voltage applied to the gate ramps up, therein mitigating delays in achieving a gate-source or gate-drain voltage equilibrium using application of the supply voltage directly to the gate. 
     
     
       13. The apparatus of  claim 11 , wherein the first circuit includes a capacitor having first and second capacitor plates, and wherein the second circuit includes:
 a first set of switches configured and arranged to connect the first capacitor plate to the supply voltage and to connect the second capacitor plate to a ground-level port, 
 a second set of switches configured and arranged to connect the first capacitor plate to the gate and to connect the second capacitor plate to the one of the source and the drain of the transistor across which the stored charged is coupled, and 
 a control circuit configured and arranged to:
 in the first mode, couple the first capacitor plate to the supply voltage and couple the second capacitor plate to a ground-level port by operating the first set of switches in a closed state and operating the second set of switches in an open state, and 
 in the second mode, couple the first capacitor plate to the gate and couple the second capacitor plate to the source or drain by operating the first set of switches in an open state and operating the second set of switches in a closed state, therein mitigating delays in a start of data flow through the source and drain of the transistor upon switching of the transistor from the off state to the on state. 
 
 
     
     
       14. The apparatus of  claim 13 , further including a delay circuit configured and arranged to delay closing of the second set of switches, upon transition from the first mode to the second mode, and to ensure that the first set of switches are switched to the open state before the second set of switches are switched to the closed state. 
     
     
       15. A method comprising:
 using a switching circuit, operating a transistor having a source and drain connected in series between an input port and an output port, and a gate that switches the transistor between an on state, in which the transistor transfers data signals received on the input port to the output port by connecting the input port to the output port, and an off state, in which the transistor disconnects the input port from the output port, by
 in a first mode, coupling a voltage across a charge storage circuit and storing a charge in the charge storage circuit while decoupling the transistor from the charge storage circuit, and 
 in a second mode, switching the transistor from the off state to the on state by coupling the stored charge across the gate and one of the source and drain of the transistor. 
 
 
     
     
       16. The method of  claim 15 , wherein storing a charge in the charge storage circuit includes storing the charge in a capacitor having first and second capacitor plates, and wherein operating the transistor includes:
 in the first mode, coupling the first capacitor plate to an input voltage supply port and coupling the second capacitor plate to a ground-level port by operating a first set of switches in a closed state and operating a second set of switches in an open state, and 
 in the second mode, coupling the first capacitor plate to the gate and coupling the second capacitor plate to the source or drain by operating the first set of switches in an open state and operating the second set of switches in a closed state, therein mitigating delays in a start of data flow through the source and drain of the transistor upon switching of the transistor from the off state to the on state. 
 
     
     
       17. The method of  claim 15 , further including ensuring non-overlapping operation of the first mode and the second mode by decoupling the voltage from the charge storage circuit, prior to coupling the stored charge across the gate and one of the source and drain of the transistor. 
     
     
       18. The method of  claim 15 , wherein:
 operating in the first mode includes disconnecting the transistor from the charge storage circuit and thereafter connecting the charge storage circuit between a voltage supply port and a ground-level port; and 
 operating in the second mode includes disconnecting the charge storage circuit from the voltage supply port and the ground-level port and thereafter connecting the charge storage circuit across the gate and source or drain. 
 
     
     
       19. The method of  claim 15 , wherein operating the transistor includes using the stored charge to mitigate delay in equilibrating the gate-source voltage or the gate-drain voltage of the transistor, as would occur upon coupling of the gate to the supply voltage without coupling the stored charge across the gate and the one of the source and drain of the transistor. 
     
     
       20. The method of  claim 15 , wherein coupling the stored charge across the gate and the one of the source and drain of the transistor includes mitigating delay in a start of data flow through the source and drain of the transistor upon switching of the transistor from the off state to the on state, by using the stored charge to set the gate-source or gate-drain voltage while coupling a bias voltage supply node to the gate that operates to ramps from a low voltage level to the bias voltage level with a time delay.