Self-aligned under bump metal

Abstract

An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

What is claimed is: 
     
       1. A method of forming an integrated circuit, comprising;
 forming an interconnect region; 
 forming a top interconnect level in the interconnect region, so that the top interconnect level includes a connection pad; 
 forming a dielectric layer over the top interconnect level; 
 forming a connection opening in the dielectric layer such that a portion of a top surface of the connection pad is exposed, while the dielectric layer overlaps a periphery of the connection pad, and such that a connection opening sidewall is formed at a boundary of the dielectric layer over the connection pad; 
 forming an under bump metal layer on the exposed portion of the top surface of the connection pad and over the dielectric layer, such that the under bump metal layer contacts the connection opening sidewall; 
 selectively removing material from the under bump metal layer over the dielectric layer so as to form a self-aligned under bump metal pad, such that the self-aligned under bump metal pad contacts the connection opening sidewall, and such that the self-aligned under bump metal pad does not contact a top surface of the dielectric layer; and 
 forming a solder ball on a top surface of the self-aligned under bump metal pad. 
 
     
     
       2. The method of  claim 1 , wherein the self-aligned under bump metal pad consists of a single layer of metal. 
     
     
       3. The method of  claim 1 , wherein the step of forming the under bump metal layer includes:
 forming at least one of a metal adhesion sub-layer and a metal blocking sub-layer, wherein the adhesion sub-layer if formed is formed on the exposed portion of the connection pad, is continuous along the connection opening sidewall, and is less than one-third as thick as the dielectric layer, and the blocking sub-layer if formed is continuous along the connection opening sidewall, and is less than one-half as thick as the dielectric layer; and 
 forming a solder connection sub-layer over the adhesion sub-layer if formed and the blocking sub-layer if formed, wherein the solder connection sub-layer is at least one-half as thick as the dielectric layer. 
 
     
     
       4. The method of  claim 3 , wherein:
 the adhesion sub-layer is formed and consists substantially of TaN; 
 the blocking sub-layer is formed and includes more than 50 percent Ni; 
 the cap sub-layer is formed and consists substantially of Pd; and 
 the step of forming the solder connection sub-layer includes a step of electroplating a Cu sub-layer. 
 
     
     
       5. The method of  claim 1 , wherein the step of forming the under bump metal layer includes:
 forming a metal adhesion sub-layer on the exposed portion of the connection pad, wherein the adhesion sub-layer is continuous along the connection opening sidewall, and is less than one-third as thick as the dielectric layer; 
 forming a metal solder connection/blocking sub-layer on the adhesion layer, wherein the solder connection/blocking sub-layer is continuous along the connection opening sidewall, and is less than one-half as thick as the dielectric layer. 
 
     
     
       6. The method of  claim 5 , wherein:
 the adhesion sub-layer consists substantially of TaN; 
 the solder connection/blocking sub-layer includes more than 50 percent Ni; and 
 the step of forming the under bump metal layer further includes forming a cap sub-layer on a top surface of the solder connection/blocking sub-layer, such that the cap sub-layer is less than one-fourth as thick as the dielectric layer, is continuous along the connection opening sidewall, and consists substantially of Pd. 
 
     
     
       7. A method of forming an integrated circuit, comprising:
 forming an interconnect region; 
 forming a top interconnect level in the interconnect region, so that the top interconnect level includes a connection pad; 
 forming a dielectric layer over the top interconnect level; 
 forming a connection opening in the dielectric layer such that a portion of a top surface of the connection pad is exposed, while the dielectric layer overlaps a periphery of the connection pad, and such that a connection opening sidewall is formed at a boundary of the dielectric layer over the connection pad; 
 forming a first metal sub-layer on the exposed portion of the top surface of the connection pad and over the dielectric layer, wherein the first sub-layer is continuous along the connection opening sidewall, and is less than one-third as thick as the dielectric layer; 
 forming a second metal sub-layer on an exposed surface of the first sub-layer, wherein the second sub-layer is continuous along the connection opening sidewall, and is less than one-third as thick as the dielectric layer; 
 selectively removing material from the first sub-layer and the second sub-layer over the dielectric layer, and such that the first sub-layer and the second sub-layer do not contact a top surface of the dielectric layer; 
 forming a metal solder connection pad on an exposed surface of the second sub-layer by a process of electroless plating; and 
 forming a solder ball on a top surface of the solder connection pad. 
 
     
     
       8. A method of forming an integrated circuit, comprising:
 forming an interconnect region; 
 forming a top interconnect level in the interconnect region, so that the top interconnect level includes a connection pad; 
 forming a dielectric layer over the top interconnect level; 
 forming a connection opening in the dielectric layer such that a portion of a top surface of the connection pad is exposed, while the dielectric layer overlaps a periphery of the connection pad, and such that a connection opening sidewall is formed at a boundary of the dielectric layer over the connection pad; 
 forming a first metal sub-layer on the exposed portion of the top surface of the connection pad and over the dielectric layer, wherein the first sub-layer is continuous along the connection opening sidewall, and is less than one-third as thick as the dielectric layer; 
 forming a second metal sub-layer on an exposed surface of the first sub-layer, wherein the second sub-layer is continuous along the connection opening sidewall, and is less than one-third as thick as the dielectric layer; 
 selectively removing material from the first sub-layer and the second sub-layer over the dielectric layer, and such that the first sub-layer and the second sub-layer do not contact a top surface of the dielectric layer; 
 forming a metal seed sub-layer on an exposed portion of the second sub-layer an over the dielectric layer; 
 forming a metal solder connection sub-layer on an exposed surface of the seed sub-layer by a process of electroplating; 
 selectively removing material from the seed sub-layer and the solder connection sub-layer over the dielectric layer, and such that the seed sub-layer and the solder connection sub-layer do not overlap the dielectric layer; and 
 forming a solder ball on a top surface of the solder connection sub-layer. 
 
     
     
       9. The method of  claim 8 , wherein:
 the first sub-layer consists substantially of TaN; 
 the second sub-layer includes more than 50 percent Ni; 
 the seed sub-layer consists substantially of Cu; and 
 the solder connection sub-layer consists substantially of Cu. 
 
     
     
       10. The method of  claim 9 , further including forming a Pd sublayer on an exposed surface of the second sub-layer, the Pd sublayer being formed prior to the step of selectively removing material from the first sub-layer and the second sub-layer.