Analog to digital converters with oversampling

Abstract

Embodiments of the invention include an oversampling Analog to Digital Converter that uses uneven non-overlapping clock phases to reduce switched capacitor circuit power consumption. A return-to-zero sub phase of one of the clock phases may also be used for feedback reference capacitors. A delay lock loop may be combined with the non-overlapping clock phase generator to control accurate timing.

What is claimed is: 
     
       1. An analog-to-digital modulator, comprising:
 a switched-capacitor loop filter, including:
 first, second, third and fourth integrators operable in a charging phase and a dumping phase, in which the first and second integrators are decoupled from the remaining third and fourth integrators during the dumping phase. 
 
 
     
     
       2. The analog-to-digital modulator according to  claim 1 , in which the charging phase is driven by a first clock and the dumping phase is driven by a second clock, and in which the first and second clocks have non-overlapping clock phases.