Semiconductor memory device and operating method thereof

Abstract

A semiconductor memory device may include a memory cell array, a peripheral circuit, a control logic, and a source line precharge path. The memory cell array may have a plurality of memory strings. The peripheral circuit may perform a program operation for the memory cell array. The control logic may control the peripheral circuit a channel precharge operation of the program operation. The source line precharge path may precharge channels of the plurality of memory strings through a source line of the memory cell array. The peripheral circuit may control, according to program data, a potential level of a selected one of a plurality of bit lines coupled to the plurality of memory strings during the channel precharge operation.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a memory cell array including a plurality of memory strings; 
 a peripheral circuit configured to perform a program operation for the memory cell array; 
 a control logic configured to control the peripheral circuit during a channel precharge operation of the program operation; and 
 a source line precharge path configured to precharge channels of the plurality of memory strings through a source line of the memory cell array, 
 wherein the peripheral circuit controls, according to program data, a potential level of a selected one of a plurality of bit lines coupled to the plurality of memory strings during the channel precharge operation, 
 wherein the peripheral circuit applies a first source line voltage to the source line during the channel precharge operation, and maintains the first source line voltage or applies a second source line voltage lower than the first source line voltage thereto when a program voltage is applied. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , wherein the plurality of memory strings are coupled between the plurality of bit lines and the source line, and wherein each of the bit lines is coupled to at least two of the memory strings. 
     
     
       3. The semiconductor memory device according to  claim 2 , wherein:
 a first memory string coupled to a first bit line of the plurality of bit lines and a second memory string coupled to a second bit line of the plurality of bit lines share a first drain select line; 
 a third memory string coupled to the first bit line and a fourth memory string coupled to the second bit line share a second drain select line; and 
 the first to fourth memory strings share a plurality of word lines. 
 
     
     
       4. The semiconductor memory device according to  claim 3 , wherein the first memory string and the fourth memory string share a first source select line, and the second memory string and the third memory string share a second source select line. 
     
     
       5. The semiconductor memory device according to  claim 4 , wherein the peripheral circuit applies a program inhibit voltage to unselected ones of the plurality of bit lines during the channel precharge operation. 
     
     
       6. The semiconductor memory device according to  claim 3 , wherein the control logic controls the peripheral circuit such that the program voltage applying operation is performed after the channel precharge operation. 
     
     
       7. The semiconductor memory device according to  claim 6 , wherein, during the program voltage applying operation, the peripheral circuit applies a control voltage to a selected one of the first and second drain select lines and applies a turn-off voltage to a remaining unselected drain select line. 
     
     
       8. The semiconductor memory device according to  claim 7 , wherein the control voltage is higher than a threshold voltage of a drain select transistor included in the plurality of memory strings and has a potential level equal to or lower than a potential level of a bit line charge voltage. 
     
     
       9. The semiconductor memory device according to  claim 7 , wherein, during the program voltage applying operation, the peripheral circuit applies a program voltage to a selected one of the plurality of word lines and applies a pass voltage to unselected ones of the word lines. 
     
     
       10. The semiconductor memory device according to  claim 9 , wherein the peripheral circuit applies the program voltage and the pass voltage to the plurality of word lines before applying the control voltage to the selected drain select line. 
     
     
       11. A method of operating a semiconductor memory device, comprising:
 providing a memory cell block including a plurality of memory strings coupled between a plurality of bit lines and one or more source lines; 
 precharging channels of the plurality of memory strings by applying a first source voltage to the one or more source lines; 
 controlling a potential level of a selected one of the bit lines according to program data while precharging the channels of the plurality of memory strings; 
 electrically coupling a selected one of the plurality of memory strings to the selected bit line and applying a program voltage thereto; and 
 lowering a voltage applied to the one or more sources lines to a second source voltage when the program voltage is applied. 
 
     
     
       12. The method according to  claim 11 , wherein, when controlling the potential level of the selected bit line, a program inhibit voltage is applied to an unselected one of the plurality of bit lines. 
     
     
       13. The method according to  claim 11 , wherein at least two memory strings are coupled to each of the plurality of bit lines, and wherein the at least two memory strings are respectively coupled to different drain select lines. 
     
     
       14. The method according to  claim 11 , wherein:
 a first memory string coupled to a first bit line of the plurality of bit lines and a second memory string coupled to a second bit line of the bit lines share a first drain select line; 
 a third memory string coupled to the first bit line and a fourth memory string coupled to the second bit line share a second drain select line; and 
 the first to fourth memory strings share a plurality of word lines. 
 
     
     
       15. The method according to  claim 14 , wherein applying the program voltage comprise applying a control voltage to a selected one of the first and second drain select lines, and applying a turn-off voltage to a remaining unselected drain select line. 
     
     
       16. A method of operating a semiconductor memory device, comprising:
 providing a memory cell block including a plurality of memory strings coupled between a plurality of bit lines and one or more source lines; 
 precharging channels of the plurality of memory strings by applying a first source voltage to the one or more source lines; 
 controlling a potential level of the bit lines according to program data while precharging the channels of the plurality of memory strings; and 
 electrically coupling a selected one of the plurality of memory strings to the bit lines, and applying a program voltage thereto; and 
 lowering a voltage applied to the one or more source lines to a second source voltage when the program voltage is applied. 
 
     
     
       17. The method according to  claim 16 , wherein bit lines to which a program inhibit voltage is applied according to the program data are electrically separated from the plurality of memory strings. 
     
     
       18. The method according to  claim 16 , wherein:
 a first memory string coupled to a first bit line of the plurality of bit lines and a second memory string coupled to a second bit line of the plurality of bit lines share a first drain select line; 
 a third memory string coupled to the first bit line and a fourth memory string coupled to the second bit line share a second drain select line; and 
 the first to fourth memory strings share a plurality of word lines. 
 
     
     
       19. The method according to  claim 18 , wherein applying the program voltage comprise applying a control voltage to a selected one of the first and second drain select lines, and applying a turn-off voltage to a remaining unselected drain select line.