Digital time converter systems and method

Abstract

A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.

What is claimed is: 
     
       1. A digital to time converter (DTC) comprising:
 a lookup table configured to generate one or more corrections based on a middle bits of an input signal; 
 a divider coarse delay component configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections; 
 a thermometric array configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections; and 
 a switched capacitor array configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits. 
 
     
     
       2. The converter of  claim 1 , wherein the lookup table includes a first table configured to generate a thermometric correction based on the thermometric bits and wherein the divider and the thermometric array utilize the thermometric correction and the thermometric bits include the middle bits. 
     
     
       3. The converter of  claim 2 , wherein the lookup table further includes a second table configured to generate an inverse binary delay correction based on the thermometric bits and the switched capacitor array is configured to utilize the inverse binary delay correction. 
     
     
       4. The converter of  claim 3 , wherein the lookup table further includes a third table configured to generate a residue correction based on the thermometric bits and the switched capacitor array is further configured to utilize the residue correction to generate the digital delay signal. 
     
     
       5. The converter of  claim 1 , wherein the coarse delay component is a multi-modulus divider (MMD). 
     
     
       6. The converter of  claim 1 , wherein the middle bits exclude a most significant bit and a least significant bit and the switched capacitor bits are least significant bits of the input signal. 
     
     
       7. The converter of  claim 1 , wherein the switched capacitor array includes a plurality of capacitors connected to an output of the array, wherein the plurality of capacitors are relatively small. 
     
     
       8. The converter of  claim 7 , wherein the switch capacitor array includes a plurality of switches each configured to selectively activate an associated capacitor of the array. 
     
     
       9. The converter of  claim 8 , further comprising a switched capacitor decoder configured to receive a fine delay signal and generate a plurality of capacitor control signals coupled to the plurality of switches. 
     
     
       10. The converter of  claim 1 , wherein the switched capacitor array has substantially linear capacitor steps. 
     
     
       11. The converter of  claim 1 , wherein the thermometric array includes a plurality of thermometric inverters. 
     
     
       12. A digital to time converter (DTC) arrangement comprising:
 a lookup table comprising a table configured to generate a residue correction based on thermometric bits of an input signal; 
 a summation component configured to combine the residue correction with a first signal based on the input signal to generate a fine delay signal; and 
 a switched capacitor array configured to generate a delay based on a medium approximation signal and the fine delay signal. 
 
     
     
       13. The arrangement of  claim 12 , further comprising a decoder configured to decode the fine delay signal into a plurality of control signals for the switched capacitor array. 
     
     
       14. The arrangement of  claim 13 , wherein each capacitor of the switched capacitor array has an associated switch configured to receive one of the plurality of control signals from the decoder. 
     
     
       15. The arrangement of  claim 12 , wherein the digital delay has a substantially finer quantization than the medium approximation signal. 
     
     
       16. The arrangement of  claim 12 , further comprising a combiner configured to generate the first signal based on the input signal and an inverse binary delay correction. 
     
     
       17. The arrangement of  claim 16 , wherein the lookup table includes a second table configured to generate the inverse binary delay correction based on the thermometric bits, wherein the thermometric bits are middle bits of the input signal. 
     
     
       18. A method of operating a digital time controller (DTC), the method comprising:
 receiving an input signal having a digital delay code, wherein the input signal comprises a plurality of bits; 
 generating one or more corrections using a lookup table based on thermometric bits of the input signal, wherein the thermometric bits are middle bits of the input signal and exclude a most significant bit and a least significant bit of the input signal; 
 dividing an oscillator signal based on a thermometric correction of the one or more corrections to generate a plurality of divider signals; 
 generating a medium approximation signal from the plurality of divider signals based on the thermometric correction; and 
 generating a digital delay from the medium approximation signal based on a residue correction of the one or more corrections using an array of switched capacitors. 
 
     
     
       19. The method of  claim 18 , wherein a multi modulus divider (MMD) is used to generate the plurality of divider signals. 
     
     
       20. The method of  claim 18 , wherein generating the digital delay is further based on an inverse binary delay correction.