Driving circuit and display device including the same

Abstract

Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

What is claimed is: 
     
       1. A scan driver comprising:
 a plurality of first unit scan driving circuits configured to receive a prior first scan signal in synchronization with a first clock signal and to respond to an enable level of the prior first scan signal to output a second clock signal as a corresponding first scan signal during one cycle of the first clock signal; and 
 a plurality of second unit scan driving circuits configured to receive the corresponding first scan signal in synchronization with a third clock signal and to respond to an enable level of the corresponding first scan signal to output a fourth clock signal as a corresponding second scan signal during one cycle of the third clock signal, 
 wherein a width of a first wire configured to transfer the third clock signal and a width of a second wire configured to transfer the fourth clock signal are larger than at least one of a width of a third wire configured to transfer the first clock signal and a width of a fourth wire configured to transfer the second clock signal. 
 
     
     
       2. The scan driver of  claim 1 , wherein
 each of the plurality of first unit scan driving circuits comprises: 
 a first transistor comprising an electrode configured to receive the second clock signal, and a gate configured to receive the prior first scan signal; 
 a second transistor comprising an electrode coupled to another electrode of the first transistor, and another electrode coupled to a first voltage; and 
 a third transistor coupled between a gate electrode of the second transistor and a second voltage and configured to be turned on according to the first clock signal. 
 
     
     
       3. The scan driver of  claim 2 , wherein a width of a fifth wire configured to transfer the first voltage is larger than a width of a sixth wire configured to transfer the second voltage. 
     
     
       4. The scan driver of  claim 1 , wherein
 each of the plurality of second unit scan driving circuits comprises: 
 a first transistor comprising an electrode configured to receive the fourth clock signal, and a gate configured to receive the corresponding first scan signal; 
 a second transistor comprising an electrode coupled to another electrode of the first transistor, and another electrode coupled to a first voltage; and 
 a third transistor coupled between a gate electrode of the second transistor and a second voltage and configured to be turned on according to the third clock signal. 
 
     
     
       5. The scan driver of  claim 4 , wherein a width of a fifth wire configured to transfer the first voltage is larger than a width of a sixth wire configured to transfer the second voltage. 
     
     
       6. A scan driver comprising:
 a first wire configured to transfer a first clock signal; 
 a second wire configured to transfer a second clock signal; 
 a third wire configured to transfer a third clock signal; 
 a first transistor comprising a gate electrode coupled to the first wire; 
 a second transistor comprising a gate electrode coupled to an electrode of the first transistor; 
 a third transistor comprising a gate electrode coupled to the third wire and an electrode coupled to an electrode of the second transistor; and 
 a fourth transistor comprising a gate electrode coupled to another electrode of the third transistor, and an electrode coupled to the second wire, 
 wherein a signal is outputted through another electrode of the fourth transistor, and a width of the second wire is larger than a width of the first wire, and 
 wherein the first transistor transmits a signal input to another electrode of the first transistor to the gate electrode of the second transistor according to the first clock signal. 
 
     
     
       7. The scan driver of  claim 6 , further comprising:
 a fifth transistor comprising a gate electrode coupled to the second wire; and 
 a sixth transistor comprising a gate electrode coupled to an electrode of the fifth transistor, and an electrode coupled to the third wire, 
 wherein another signal is outputted through another electrode of the sixth transistor, and a width of the third wire is larger than the width of the first wire. 
 
     
     
       8. The scan driver of  claim 6 , further comprising:
 a seventh transistor comprising a gate electrode, an electrode coupled to another electrode of the fourth transistor, and another electrode coupled to a fourth wire configured to transfer a first voltage; and 
 an eighth transistor comprising a gate electrode coupled to the gate electrode of the third transistor, an electrode coupled to a fifth wire configured to transfer a second voltage, and another electrode coupled to the gate electrode of the seventh transistor, 
 wherein a width of the fourth wire is larger than a width of the fifth wire. 
 
     
     
       9. A display device comprising:
 a scan driver configured to generate a plurality of first scan signals and a plurality of second scan signals; and 
 a plurality of pixels configured to receive a plurality of data voltages according to the plurality of second scan signals, and to be initialized according to the plurality of first scan signals, 
 wherein the scan driver comprises:
 a plurality of first unit scan driving circuits configured to receive a prior first scan signal in synchronization with a first clock signal and to respond to an enable level of the prior first scan signal to output a second clock signal as a corresponding first scan signal during one cycle of the first clock signal; and 
 a plurality of second unit scan driving circuits configured to receive the corresponding first scan signal in synchronization with a third clock signal and to respond to an enable level of the corresponding first scan signal to output a fourth clock signal as a corresponding second scan signal during one cycle of the third clock signal, 
 wherein a width of a first wire configured to transfer the third clock signal and a width of a second wire configured to transfer the fourth clock signal are larger than at least one of a width of a third wire configured to transfer the first clock signal and a width of a fourth wire configured to transfer the second clock signal. 
 
 
     
     
       10. The display device of  claim 9 , wherein
 each of the plurality of first unit scan driving circuits comprises: 
 a first transistor comprising an electrode configured to receive the second clock signal, and a gate configured to receive the prior first scan signal; 
 a second transistor comprising an electrode coupled to another electrode of the first transistor, and another electrode coupled to a first voltage; and 
 a third transistor coupled between a gate electrode of the second transistor and a second voltage, and configured to be turned on according to the first clock signal. 
 
     
     
       11. The display device of  claim 9 , wherein:
 each of the plurality of second unit scan driving circuits comprises: 
 a first transistor comprising an electrode configured to receive the fourth clock signal, and a gate configured to receive the corresponding first scan signal; 
 a second transistor comprising an electrode coupled to another electrode of the first transistor, and another electrode coupled to a first voltage; and 
 a third transistor coupled between a gate electrode of the second transistor and a second voltage, and configured to be turned on according to the third clock signal.