Semiconductor integrated circuit device, power supply device, and method of controlling power supply device

Abstract

A conventional power supply device has a problem in miniaturization. A power supply device generates a prediction value of an error signal from first and second error signals, and controls an output voltage so that the prediction value lies between first and second threshold values. The first error signal is obtained by converting an error voltage based on the difference between the output voltage and a reference voltage at a first timing. The second error signal is obtained by converting an error voltage based on the difference between the output voltage and the reference voltage at a second timing.

What is claimed is: 
     
       1. A power supply device comprising:
 a semiconductor integrated circuit device having a target voltage generating circuit configured to generate a target voltage, a differential amplifier configured to output an error voltage based on the difference between an output voltage and the target voltage, an analog-to-digital (AD) converter configured to convert the error voltage to a digital value and output the digital value as an error signal, and a digital controller configured to output a control signal based on the error signal; 
 a driver configured to output a drive signal based on the control signal; 
 a switching element which is switching controlled by the drive signal; and 
 a smoothing circuit configured to smooth voltage supplied from the switching element and output the smoothed voltage as the output voltage, 
 wherein the AD converter converts a first error voltage as the error voltage to a digital voltage to generate a first error signal as the error signal at a first timing and converts a second error voltage as the error voltage to a digital value to generate a second error signal as the error signal at a second timing before the first timing, and 
 wherein the timing controller generates a prediction value of the error signal at a third timing which is later than the first timing in accordance with the first and second error signals and generates the control signal so that the prediction value lies between a first control threshold and a second control threshold smaller than the first control threshold. 
 
     
     
       2. A power supply device comprising:
 a semiconductor integrated circuit device having a target voltage generating circuit configured to generate a target voltage, a differential amplifier configured to output an error voltage based on the difference between an output voltage and the target voltage, an analog-to-digital (AD) converter configured to convert the error voltage to a digital value and output the digital value as an error signal, and a digital controller configured to output a control signal based on the error signal; 
 a driver configured to output a drive signal based on the control signal; 
 a switching element which is switching controlled by the drive signal; and 
 a smoothing circuit configured to smooth voltage supplied from the switching element and output the smoothed voltage as the output voltage, 
 wherein the AD converter converts a first error voltage as the error voltage to a digital voltage to generate a first error signal as the error signal at a first timing and converts a second error voltage as the error voltage to a digital value to generate a second error signal as the error signal at a second timing before the first timing, and 
 wherein the timing controller generates a prediction value of the error signal at a third timing which is later than the first timing in accordance with the first and second error signals and generates the control signal so that the prediction value lies between a first control threshold and a second control threshold smaller than the first control threshold, 
 wherein the digital controller determines an erroneous operation when the first error signal is larger than the first control threshold and the prediction value is smaller than the second control threshold or when the first error signal is smaller than the second control threshold and the prediction value is larger than the first control threshold, and outputs the determination result. 
 
     
     
       3. The power supply device according to  claim 2 ,
 wherein the digital controller determines a first erroneous operation mode as the erroneous operation when the first error signal is larger than the first control threshold and the prediction value is smaller than the second control threshold, and determines a second erroneous operation mode as the erroneous operation when the first error signal is smaller than the second control threshold and the prediction value is larger than the first control threshold, 
 wherein the digital controller controls to decrease the output voltage by the control signal in the first erroneous operation mode, and 
 wherein the digital controller controls to increase the output voltage by the control signal in the second erroneous operation mode. 
 
     
     
       4. The power supply device according to  claim 1 , wherein a frequency of sampling the error voltage of the AC converter is higher than a switching frequency of the switching element. 
     
     
       5. The power supply device according to  claim 2 , wherein the digital controller further comprises a first register for setting the first control threshold, a second register for setting the second control threshold, and a third register for setting a length of a prediction period between the first error signal and the prediction value. 
     
     
       6. The power supply device according to  claim 5 , wherein when the erroneous operation is detected, a value in at least any of the first, second, and third registers is rewritten from the outside. 
     
     
       7. The power supply device according to  claim 5 , wherein an AD conversion range of the AD converter is according to ranges in which the first and second control thresholds can be set. 
     
     
       8. The power supply device according to  claim 1 ,
 wherein the digital controller further comprises a first retention circuit configured to retain the error signals of N−1 (N denotes a natural number of three or larger) generated at timings different by sampling cycles of the AD converter, and 
 wherein the digital controller generates the prediction value by performing prediction arithmetic operation approximated to an (N−1)th curve using the error signals generated by the AD converter and the N−1 error signals retained in the first retention circuit. 
 
     
     
       9. The power supply device according to  claim 1 ,
 wherein the digital controller further comprises a second retention circuit configured to retain “c” (c denotes a natural number of two or larger) pieces of the error signals generated at timings different by sampling cycles of the AD converter, and 
 wherein the digital controller generates an averaged error signal on the basis of the error signal generated by the AD converter and the error signal retained in the second retention circuit, and generates a prediction value by using the averaged error signal. 
 
     
     
       10. The power supply device according to  claim 9 , further comprising a fourth register for setting “c” as an averaging number for generating the averaged prediction value. 
     
     
       11. The power supply device according to  claim 1 ,
 wherein the digital controller comprises a Proportional Integral and Differential (PID) control circuit configured to perform control so that the error signal from the AD converter becomes close to zero, a pulse width modulation (PWM) signal generating circuit configured to generate a PWM signal based on an output from the PID control circuit, a high-level signal generating circuit configured to generate and output a high-level signal, a low-level signal generating circuit configured to generate and output a low-level signal, and a selector configured to select any of an output of the PWM signal from the PWM signal generating circuit, an output of the high-level signal from the high-level signal generating circuit, and an output of the low-level signal from the low-level signal generating circuit and configured to output the selected signal as the control signal, and 
 wherein the digital controller controls so that the high-level signal is output by the selector when the prediction value is smaller than the second control threshold, controls so that the PWM signal is output by the selector when the prediction value is larger than the second control threshold and is smaller than the first control threshold, and controls so that the low-level signal is output by the selector when the prediction value is larger than the first control threshold. 
 
     
     
       12. A semiconductor integrated circuit device comprising:
 a target voltage generating circuit configured to generate a target voltage; 
 a differential amplifier configured to output an error voltage based on the difference between an output voltage and the target voltage; 
 an analog-to-digital (AD) converter configured to convert the error voltage to a digital value and output the digital value as an error signal; and 
 a digital controller configured to output a control signal based on the error signal, 
 wherein the AD converter converts a first error voltage as the error voltage to a digital voltage to generate a first error signal as the error signal at a first timing and converts a second error voltage as the error voltage to a digital value to generate a second error signal as the error signal at a second timing before the first timing, 
 wherein the digital controller generates a prediction value of the error signal at a third timing as a timing later than the first timing in accordance with the first and second error signals, and generates the control signal so that the prediction value lies between a first control threshold and a second control threshold smaller than the first control threshold, and 
 wherein the control signal is supplied to a driver for generating a drive signal for a switching element which supplies a voltage to a smoothing circuit for outputting the output voltage in order to generate the drive signal. 
 
     
     
       13. The semiconductor integrated circuit device according to  claim 12 , wherein the digital controller determines an erroneous operation when the first error signal is larger than the first control threshold and the prediction value is smaller than the second control threshold or when the first error signal is smaller than the second control threshold and the prediction value is larger than the first control threshold, and outputs the determination result. 
     
     
       14. The semiconductor integrated circuit device according to  claim 13 ,
 wherein the digital controller determines a first erroneous operation mode as the erroneous operation when the first error signal is larger than the first control threshold and the prediction value is smaller than the second control threshold, and determines a second erroneous operation mode as the erroneous operation when the first error signal is smaller than the second control threshold and the prediction value is larger than the first control threshold, 
 wherein the digital controller controls to decrease the output voltage by the control signal in the first erroneous operation mode, and 
 wherein the digital controller controls to increase the output voltage by the control signal in the second erroneous operation mode. 
 
     
     
       15. The semiconductor integrated circuit device according to  claim 12 , wherein a frequency of sampling the error voltage of the AC converter is higher than a switching frequency of the switching element. 
     
     
       16. The semiconductor integrated circuit device according to  claim 13 , wherein the digital controller further comprises a first register for setting the first control threshold, a second register for setting the second control threshold, and a third register for setting a length of a prediction period between the first error signal and the prediction value. 
     
     
       17. The semiconductor integrated circuit device according to  claim 16 , wherein when the erroneous operation is detected, a value in at least any of the first, second, and third registers is rewritten from the outside. 
     
     
       18. The semiconductor integrated circuit device according to  claim 16 , wherein an AD conversion range of the AD converter is according to ranges in which the first and second control thresholds can be set. 
     
     
       19. The semiconductor integrated circuit device according to  claim 12 ,
 wherein the digital controller further comprises a first retention circuit configured to retain N−1 (N denotes a natural number of three or larger) pieces of error signals generated at timings which vary by sampling cycles of the AD converter, and 
 wherein the digital controller generates the prediction value by performing prediction arithmetic operation approximated to an (N−1)th curve using the error signals generated by the AD converter and N−1 pieces of the error signals retained in the first retention circuit. 
 
     
     
       20. The semiconductor integrated circuit device according to  claim 12 ,
 wherein the digital controller further comprises a second retention circuit configured to retain “c” (c denotes a natural number of two or larger) pieces of the error signals generated at timings which vary by sampling cycles of the AD converter, and 
 wherein the digital controller generates an averaged error signal based on the error signal generated by the AD converter and the error signal retained in the second retention circuit, and generates the prediction value by using the averaged error signal. 
 
     
     
       21. The semiconductor integrated circuit according to  claim 20 , further comprising a fourth register for setting “c” as an averaging number for generating the averaged prediction value. 
     
     
       22. The semiconductor integrated circuit device according to  claim 12 ,
 wherein the digital controller comprises a Proportional Integral and Differential (PID) control circuit configured to perform control so that the error signal from the AD converter becomes close to zero, a pulse width modulation (PWM) signal generating circuit configured to generate a PWM signal based on an output from the PID control circuit, a high-level signal generating circuit configured to generate and output a high-level signal, a low-level signal generating circuit configured to generate and output a low-level signal, and a selector configured to select any of an output of the PWM signal from the PWM signal generating circuit, an output of the high-level signal from the high-level signal generating circuit, and an output of the low-level signal from the low-level signal generating circuit and configured to output the selected signal as the control signal, and 
 wherein the digital controller controls so that the high-level signal is output by the selector when the prediction value is smaller than the second control threshold, controls so that the PWM signal is output by the selector when the prediction value is larger than the second control threshold and is smaller than the first control threshold, and controls so that the low-level signal is output by the selector when the prediction value is larger than the first control threshold. 
 
     
     
       23. A power supply device comprising:
 a plurality of power supply circuits each outputting output voltage; each of the power supply circuits comprising:
 a target voltage generating circuit configured to generate a target voltage, 
 a differential output circuit configured to output an error voltage based on the difference between the output voltage and the target voltage, 
 a driver configured to output a drive signal based on the control signal, 
 a switching element which is switching controlled by the drive signal, and 
 a smoothing circuit configured to smooth voltage supplied from the switching element and outputting the smoothed voltage as the output voltage; 
 
 an analog-to-digital (AD) converter that converts the error voltage to a digital value and outputs the digital value as an error signal; and 
 a digital controller that generates a prediction value of the error signal in accordance with the first and second error signals, generates the control signal so that the prediction value lies between a first control threshold and a second control threshold smaller than the first control threshold, and outputs the control signal to the driver, the first error signal being generated by converting the error voltage to a digital value at a first timing, the second error signal being generated by converting the error voltage to a digital value at a second timing as a timing before the first timing, and 
 wherein the prediction value is obtained at a third timing as a timing later than the first timing. 
 
     
     
       24. The power supply device according to  claim 16 , wherein the AD converter outputs the error signals corresponding to the plurality of power supply circuits to the digital controller in a time sharing manner,
 wherein the digital controller has setting circuits at least of the number equal to that of the plurality of power supply circuits each having a first register storing the first control threshold, a second register storing the second control threshold, and a third register storing length of a prediction period between the first error signal and the prediction value, and 
 wherein the digital controller generates the control signal corresponding to each of the plurality of power supply circuits by using values of the registers of the setting circuits corresponding to the plurality of power supply circuits. 
 
     
     
       25. The power supply device according to  claim 24 ,
 wherein the digital controller has a processor; 
 wherein the digital controller further comprises a sequencer configured to set a first generation cycle of the control signal for the first load and a second generation cycle of the control signal for the second load and configured to set a priority of generation of the control signal for the first load and generation of the control signal for the second load, and 
 when an interrupt request signal is output to the processor based on data set in the sequencer, the control signals corresponding to the plurality of power supply circuits are generated by the digital controller. 
 
     
     
       26. The power supply device according to  claim 23 , wherein the digital controller determines an erroneous operation when the first error signal is larger than the first control threshold and the prediction value is smaller than the second control threshold or when the first error signal is smaller than the second control threshold and the prediction value is larger than the first control threshold, and outputs the determination result. 
     
     
       27. The power supply device according to  claim 26 , wherein the digital controller determines a first erroneous operation mode as the erroneous operation when the first error signal is larger than the first control threshold and the prediction value is smaller than the second control threshold, and determines a second erroneous operation mode as the erroneous operation when the first error signal is smaller than the second control threshold and the prediction value is larger than the first control threshold,
 wherein the digital controller controls to decrease the output voltage by the control signal in the first erroneous operation mode, and 
 wherein the digital controller controls to increase the output voltage by the control signal in the second erroneous operation mode. 
 
     
     
       28. The power supply device according to  claim 23 , wherein a frequency of sampling the error voltage of the AC converter is higher than a switching frequency of the switching element. 
     
     
       29. The power supply device according to  claim 26 , wherein the digital controller further comprises a first register for setting the first control threshold, a second register for setting the second control threshold, and a third register for setting a length of a prediction period between the first error signal and the prediction value. 
     
     
       30. The power supply device according to  claim 29 , wherein when the erroneous operation is detected, a value in at least any of the first, second, and third registers is rewritten from the outside. 
     
     
       31. The power supply device according to  claim 29 , wherein an AD conversion range of the AD converter is according to ranges in which the first and second control thresholds can be set.