Vertical integration of hybrid waveguide with controlled interlayer thickness

Abstract

A silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO 2 overlying the first plurality of Si waveguides and a second plurality of Si 3 N 4 waveguides formed on the first layer of SiO 2 . At least one Si 3 N 4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO 2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO 2 overlying the second plurality of Si 3 N 4 waveguides. The method of accurately controlling the coupling interlayer SiO 2 thickness includes a multilayer SiO 2 /Si 3 N 4 /SiO 2 hard mask process for SiO 2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.

What is claimed is: 
     
       1. A method for forming vertically integrated hybrid waveguides with interlayer thickness control, the method comprising multiple steps in a sequential order of:
 (1) providing a silicon-on-insulator (SOI) substrate; 
 (2) forming a multi-layer hard mask overlying the SOI substrate, the multi-layer hard mask comprising a top silicon oxide layer overlying a silicon nitride layer overlying a first silicon oxide layer; 
 (3) forming one or more silicon waveguide patterns in the SOI substrate, each silicon waveguide pattern carrying the multi-layer hard mask on top of at least one silicon waveguide; 
 (4) forming a dielectric layer to overlay the one or more silicon waveguide patterns and cover any gaps separating the one or more silicon waveguide patterns; 
 (5) removing at least partially the dielectric layer to expose the multi-layer hard mask overlying the at least one silicon waveguide; 
 (6) removing at least partially the multi-layer hard mask to leave substantially the first silicon oxide layer overlying the at least one silicon waveguide; 
 (7) forming a second silicon oxide layer overlying the first silicon oxide layer such that total thickness of the first silicon oxide layer and the second silicon oxide layer is controlled to be no greater than 90 nm across entire area of the SOI substrate; 
 (8) forming one or more silicon nitride waveguides, at least one of the one or more silicon nitride waveguides overlying the second silicon oxide layer at least vertically overlapping with the at least one silicon waveguide. 
 
     
     
       2. The method of  claim 1  wherein forming the multi-layer hard mask comprises depositing by PECVD with film thickness control of about 10% margin to sequentially form a top silicon oxide layer of 30 nm overlying the silicon nitride layer of 40 nm or less overlying the first silicon oxide layer of 30 nm or less. 
     
     
       3. The method of  claim 1  wherein forming the multi-layer hard mask comprises patterning the multi-layer hard mask to define strip shapes for the one or more silicon waveguide patterns. 
     
     
       4. The method of  claim 3  wherein forming one or more silicon waveguide patterns comprises etching through a total thickness of silicon in the SOI substrate based on the strip shapes defined by the multi-layer hard mask with the top silicon oxide layer as an etching mask. 
     
     
       5. The method of  claim 4  wherein forming one or more silicon waveguide patterns comprises further etching partially through the total thickness of at least one of the one or more silicon waveguide patterns in strip shape to form a silicon rib waveguide with at least one extra step in the strip shape. 
     
     
       6. The method of  claim 1  wherein forming a dielectric layer comprises depositing silicon oxide material up to a thickness about twice of thickness of silicon in the SOI substrate. 
     
     
       7. The method of  claim 1  wherein removing at least partially the dielectric layer comprises applying a patterned etch mask and performing reverse etching to remove at least a portion of the dielectric layer with the top silicon oxide layer of the multi-layer hard mask as an etch-stopper on top of each of the one or more silicon waveguides. 
     
     
       8. The method of  claim 7  further comprising removing remaining portions of the dielectric layer by touch-up CMP polishing with the silicon nitride layer of the multi-layer hard mask as a stopper to form a planar surface substantially leveling with the silicon nitride layer of the multi-layer hard mask. 
     
     
       9. The method of  claim 1  wherein removing at least partially the multi-layer hard mask comprises using phosphoric acid (H 3 PO 4 ) hot bath to remove the silicon nitride layer while keeping substantially the first silicon oxide layer of the multi-layer hard mask. 
     
     
       10. The method of  claim 1  wherein forming a second silicon oxide layer comprises using PECVD process to deposit silicon oxide material with thickness control of 10% margin to ensure that the total thickness of silicon oxide material above the one or more silicon waveguides is about 80 nm±10 nm. 
     
     
       11. The method of  claim 1  wherein forming one or more silicon nitride waveguides comprises forming strip shaped silicon nitride waveguides with a thickness of about 400 nm. 
     
     
       12. The method of  claim 1  wherein the one or more silicon nitride waveguides comprises at least one silicon nitride waveguide disposed not overlapped with any one of the one or more silicon waveguides. 
     
     
       13. The method of  claim 1  further comprising forming a dielectric material to fully embed the one or more silicon nitride waveguides partially over the one or more silicon waveguides in the SOI substrate.