Semiconductor device and semiconductor system

Abstract

A semiconductor system may include a first semiconductor device configured to output commands, addresses and data. The semiconductor system may include a second semiconductor device configured to convert a logic level combination of the data when only any one of bits of the data is a different logic level, and store the data in response to the commands and the addresses, in a write operation.

What is claimed is: 
     
       1. A semiconductor system comprising:
 a first semiconductor device configured to output commands, addresses and data; and 
 a second semiconductor device configured to convert a logic level combination of the data in response to a flag signal which is enabled in the case where only any one of bits of the data is a different logic level, and store the data in response to the commands and the addresses, in a write operation. 
 
     
     
       2. The semiconductor system according to  claim 1 , wherein the second semiconductor device stores the data without converting the logic level combination of the data when two or more of the bits of the data are at the same logic level, in the write operation. 
     
     
       3. The semiconductor system according to  claim 1 , wherein the second semiconductor device outputs the stored data by recovering the logic level combination of the stored data, in response to an internal flag signal which is generated from the flag signal, in a read operation. 
     
     
       4. The semiconductor system according to  claim 1 , wherein the second semiconductor device comprises:
 an address generation block configured to decode the commands and the addresses, and generate row addresses and column addresses; 
 a data input/output block configured to output the data to input/output lines in the write operation, and output internal data loaded on the input/output lines, as the data, in the read operation; 
 a pattern control block configured to output the data loaded on the input/output lines to global lines by converting the logic level combination of the data or output the data loaded on the input/output lines to the global lines, in the write operation, and output the internal data loaded on the global lines to the input/output lines by recovering a logic level combination of the internal data, in the read operation; 
 a sense amplifier configured to generate the internal data in response to the data loaded on the global lines according to the row addresses and the column addresses, in the write operation, and output the internal data to the global lines, in the read operation; and 
 a memory region configured to store the internal data in memory cells selected according to the row addresses and the column addresses, in the write operation, and output the internal data stored in the memory cells selected according to the row addresses and the column addresses, in the read operation. 
 
     
     
       5. The semiconductor system according to  claim 4 , wherein the pattern control block comprises:
 a pattern detection circuit configured to detect the logic level combination of the data loaded on the input/output lines, and generate the flag signal; and 
 a pattern conversion circuit configured to output the data loaded on the input/output lines to the global lines by converting the logic level combination of the data or output the data to the global lines, in response to the flag signal, in the write operation. 
 
     
     
       6. The semiconductor system according to  claim 5 , wherein the pattern conversion circuit outputs the internal data loaded on the global lines to the input/output lines by converting the logic level combination of the internal data or output the internal data to the input/output lines, in response to an internal flag signal which is generated from the flag signal, in the read operation. 
     
     
       7. The semiconductor system according to  claim 5 , wherein the pattern detection circuit comprises:
 a first detecting section configured to generate a first pre-flag signal which is enabled when any one of the bits of the data loaded on the input/output lines is a first logic level; 
 a second detecting section configured to generate a second pre-flag signal which is enabled when any one of the bits of the data loaded on the input/output lines is a second logic level; and 
 a flag signal generating section configured to generate the flag signal which is enabled when any one of the first pre-flag signal and the second pre-flag signal is enabled. 
 
     
     
       8. The semiconductor system according to  claim 5 , wherein the pattern conversion circuit comprises:
 an input converting section configured to output the data loaded on the input/output lines to the global lines by converting the logic level combination of the data or output the data loaded on the input/output lines to the global lines, in response to the flag signal, in the write operation; and 
 an output converting section configured to output the internal data loaded on the global lines to the input/output lines by converting the logic level combination of the internal data or output the internal data loaded on the global lines to the input/output lines, in response to the internal flag signal loaded on a flag line, in the read operation. 
 
     
     
       9. The semiconductor system according to  claim 8 , wherein the input converting section comprises:
 a first converting part configured to generate input data by converting the logic level combination of the data loaded on the input/output lines, in response to the flag signal; and 
 a first buffer part configured to buffer the data loaded on the input/output lines and output the buffered data to the global lines or buffer the input data and output the buffered input data to the global lines, in response to the flag signal. 
 
     
     
       10. The semiconductor system according to  claim 8 , wherein the output converting section comprises:
 a second converting part configured to generate output data by converting the logic level combination of the internal data loaded on the global lines, in response to the internal flag signal; and 
 a second buffer part configured to buffer the internal data loaded on the global lines and output the buffered internal data to the input/output lines or buffer the output data and output the buffered output data to the input/output lines, in response to the internal flag signal. 
 
     
     
       11. The semiconductor system according to  claim 4 , further comprising:
 a driver configured to generate the internal flag signal in response to the flag signal loaded on the flag line in the write operation, and output the internal flag signal to the flag line in the read operation; and 
 a flag signal storage block configured to store the internal flag signal in the write operation, and output the internal flag signal in the read operation. 
 
     
     
       12. A semiconductor device comprising:
 a data input/output block configured to output data inputted from an exterior, to input/output lines, in a write operation, and output internal data loaded on the input/output lines, as the data, in a read operation; and 
 a pattern control block configured to output the data loaded on the input/output lines to global lines by converting a logic level combination of the data, when only any one of bits of the data is a different logic level, and output the internal data loaded on the global lines to the input/output lines by recovering a logic level combination of the internal data, in the read operation. 
 
     
     
       13. The semiconductor device according to  claim 12 , wherein the pattern control block is configured to output the data loaded on the input/output lines to the global lines by converting the logic level combination of the data, in response to a flag signal which is enabled when only any one of the bits of the data is at the different logic level. 
     
     
       14. The semiconductor device according to  claim 12 , wherein the pattern control block outputs the data to the global lines without converting the logic level combination of the data when two or more of the bits of the data are at the same logic level, in the write operation. 
     
     
       15. The semiconductor device according to  claim 13 , wherein the pattern control block comprises:
 a pattern detection circuit configured to detect the logic level combination of the data loaded on the input/output lines, and generate the flag signal; and 
 a pattern conversion circuit configured to output the data loaded on the input/output lines to the global lines by converting the logic level combination of the data or output the data to the global lines, in response to the flag signal, in the write operation. 
 
     
     
       16. The semiconductor device according to  claim 15 , wherein the pattern conversion circuit outputs the internal data loaded on the global lines to the input/output lines by converting the logic level combination of the internal data or output the internal data to the input/output lines, in response to an internal flag signal which is generated from the flag signal, in the read operation. 
     
     
       17. The semiconductor device according to  claim 13 , wherein the pattern detection circuit comprises:
 a first detecting section configured to generate a first pre-flag signal which is enabled when any one of the bits of the data loaded on the input/output lines is a first logic level; 
 a second detecting section configured to generate a second pre-flag signal which is enabled when any one of the bits of the data loaded on the input/output lines is a second logic level; and 
 a flag signal generating section configured to generate the flag signal which is enabled when any one of the first pre-flag signal and the second pre-flag signal is enabled. 
 
     
     
       18. The semiconductor device according to  claim 13 , wherein the pattern conversion circuit comprises:
 an input converting section configured to output the data loaded on the input/output lines to the global lines by converting the logic level combination of the data or output the data loaded on the input/output lines to the global lines, in response to the flag signal, in the write operation; and 
 an output converting section configured to output the internal data loaded on the global lines to the input/output lines by converting the logic level combination of the internal data or output the internal data loaded on the global lines to the input/output lines, in response to the internal flag signal loaded on a flag line, in the read operation. 
 
     
     
       19. The semiconductor device according to  claim 18 , wherein the input converting section comprises:
 a first converting part configured to generate input data by converting the logic level combination of the data loaded on the input/output lines, in response to the flag signal; and 
 a first buffer part configured to buffer the data loaded on the input/output lines and output the buffered data to the global lines or buffer the input data and output the buffered input data to the global lines, in response to the flag signal. 
 
     
     
       20. The semiconductor device according to  claim 18 , wherein the output converting section comprises:
 a second converting part configured to generate output data by converting the logic level combination of the internal data loaded on the global lines, in response to the internal flag signal; and 
 a second buffer part configured to buffer the internal data loaded on the global lines and output the buffered internal data to the input/output lines or buffer the output data and output the buffered output data to the input/output lines, in response to the internal flag signal. 
 
     
     
       21. The semiconductor device according to  claim 13 , further comprising:
 a sense amplifier configured to generate the internal data in response to the data loaded on the global lines according to row addresses and column addresses, in the write operation, and output the internal data to the global lines, in the read operation; 
 a memory region configured to store the internal data in memory cells selected according to the row addresses and the column addresses, in the write operation, and output the internal data stored in the memory cells selected according to the row addresses and the column addresses, in the read operation; 
 a driver configured to generate the internal flag signal in response to the flag signal loaded on the flag line in the write operation, and output the internal flag signal to the flag line in the read operation; and 
 a flag signal storage block configured to store the internal flag signal in the write operation, and output the internal flag signal in the read operation.