US9679898B2ActiveUtilityA1

Semiconductor device having metal gate

71
Assignee: UNITED MICROELECTRONICS CORPPriority: Jul 23, 2015Filed: Nov 1, 2016Granted: Jun 13, 2017
Est. expiryJul 23, 2035(~9 yrs left)· nominal 20-yr term from priority
H10P 50/667H10D 64/01318H01L 21/32134H01L 21/8238H01L 21/28088H01L 21/823842H01L 29/4966H01L 27/092H01L 27/0922H01L 29/49H01L 29/513H01L 29/517H01L 29/66545H10D 84/0165H10D 84/014H10D 64/685H10D 64/66H10D 84/856H10D 84/0177H10D 84/038H10D 64/691H10D 64/667H10D 64/017H10D 84/85
71
PatentIndex Score
1
Cited by
14
References
6
Claims

Abstract

A semiconductor device having metal gate includes a first metal gate structure and a second metal gate structure disposed in a first device region and in a second device region on a substrate respectively. The first metal gate structure includes a gate insulating layer, a first bottom barrier layer, a top barrier layer, and a metal layer disposed on the substrate in order, wherein the top barrier layer is directly in contact with the first bottom barrier layer. The second metal gate structure includes the gate insulating layer, a second bottom barrier layer, the top barrier layer, and the metal layer on the substrate in order, wherein the top barrier layer is directly in contact with the second bottom barrier layer. The first bottom barrier layer and the second bottom barrier layer have different impurity compositions.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device having metal gate, comprising:
 a substrate; 
 a first metal gate structure, disposed in a first device region on the substrate, the first metal gate structure comprising:
 a gate insulating layer and a first bottom barrier layer disposed on the substrate in order; 
 a top barrier layer, disposed on a surface of the first bottom barrier layer and directly in contact with the first bottom barrier layer; and 
 a metal layer, disposed on the top barrier layer; and 
 
 a second metal gate structure, disposed in a second device region on the substrate, the second metal gate structure comprising:
 the gate insulating layer and a second bottom barrier layer on the substrate in order, wherein the first bottom barrier layer and the second bottom barrier layer have different impurity compositions; 
 the top barrier layer, disposed on the second bottom barrier layer and directly in contact with the second bottom barrier layer; and 
 the metal layer disposed on the top barrier layer. 
 
 
     
     
       2. The semiconductor device having metal gate according to  claim 1 , wherein the first bottom barrier layer and the second bottom barrier layer include different contents of aluminum atom. 
     
     
       3. The semiconductor device having metal gate according to  claim 1 , wherein the first bottom barrier layer and the second bottom barrier layer have different concentration gradients of aluminum atom. 
     
     
       4. The semiconductor device having metal gate according to  claim 1 , wherein the first bottom barrier layer and the second bottom barrier are respectively a multi-layer structure. 
     
     
       5. The semiconductor device having metal gate according to  claim 4 , wherein each of the multi-layer structures is a TiN/TaN stacking layer and the top barrier layer is a titanium nitride layer. 
     
     
       6. The semiconductor device having metal gate according to  claim 1 , wherein the first metal gate structure is a P-type metal gate of a P-type transistor, the second metal gate structure is an N-type metal gate of an N-type transistor, and a content of aluminum atom of the first bottom barrier layer is less than a content of aluminum atom of the second bottom barrier layer.

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