Background calibration of interleaved timing errors in digital to analog converters

Abstract

System and method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), according to which a set of two samplers with adjustable sample time and threshold are introduced at the output of the DAC, which are separated in time. The set of samplers is swept through a n unit interval (UI) window and the n-UI window is classified to periods of transitions and non-transitions on an eye diagram. The relative timing of the lower rate clocks into an n:1 multiplexer is controlled using a control loop, to force equal eye width within the n-UI window and the interleaved timing errors are measured and corrected, until the uneven distribution is being reduced below a predetermined level.

The invention claimed is: 
     
       1. A method for the calibration of interleave time errors in an n-level PAM Digital to Analog Converter (DAC), comprising:
 a) introducing a set of two samplers with adjustable sample time and threshold, at the output of said DAC, which are separated in time; 
 b) sweeping said set of samplers through a n unit interval (UI) window; 
 c) classifying said n-UI window to periods of transitions and non-transitions on an eye diagram; 
 d) controlling the relative timing of the lower rate clocks into an n:1 multiplexer using a control loop, to force equal eye width within said n-UI window; and 
 e) measuring and correcting the interleaved timing errors, until the uneven distribution is being reduced below a predetermined level. 
 
     
     
       2. A method according to  claim 1 , wherein sweeping the two samplers is done using a plesiochronous clock signal for the two samplers. 
     
     
       3. A method according to  claim 1 , wherein the output of the two samplers is XOR-ed, in order to measure the interleaved timing errors. 
     
     
       4. A system for calibrating interleaved timing errors in a n-level PAM DAC, comprising:
 a) two samplers for sampling the output of said DAC; 
 b) a XOR gate for receiving the output of said two samplers and for detecting transition and non-transition time slots; 
 c) circuitry for detecting and measuring uneven distribution of non-transition time-slots within n-UIs; and 
 d) circuitry for adjusting clock signal timing of an erroneous UI, until said uneven distribution is being reduced below a predetermined level. 
 
     
     
       5. A system according to  claim 4 , in which the two samplers are swept using a plesiochronous clock signal for the two samplers. 
     
     
       6. A system according to  claim 4 , further comprising a XOR gate for XOR-ing the output of the two samplers, in order to measure the interleaved timing errors.