Driving circuit with adjustable termination resistor

Abstract

An embodiment of a driving circuit is provided. The driving circuit is coupled to an I/O pad. The driving circuit includes an output driver, a first termination resistor, a second termination resistor and a monitoring circuit. The output driver outputs an output data via the I/O pad. The first termination resistor and the second termination resistor are coupled to a node between the output driver and the I/O pad. The monitoring circuit monitors a first current passing through the first termination resistor and adjusts resistance of the first termination resistor and the second termination resistor according to the first current.

What is claimed is: 
     
       1. A driving circuit coupled to an I/O pad, comprising:
 an output driver configured to output data via the I/O pad; 
 a first termination resistor; 
 a second termination resistor, wherein first termination resistor and the second termination resistor are coupled to a node between the output driver and the I/O pad; and 
 a monitoring circuit configured to monitor a first current passing through the first termination resistor and adjust resistances of the first termination resistor and the second termination resistor according to the first current; 
 wherein at least one of the first termination resistor and the second termination resistor comprises a resistor with a fixed resistance and a resistive memory which is coupled to the resistor in parallel. 
 
     
     
       2. The driving circuit as claimed in  claim 1 , wherein the resistive memory comprises a resistive memory element and a transistor, and the monitoring circuit transmits a control signal to the transistor to adjust resistance of the resistive memory element. 
     
     
       3. The driving circuit as claimed in  claim 2 , wherein the control signal comprises a plurality of voltage pulse signals, and the resistance of the resistive memory element is changed according to the number of received voltage pulse signals. 
     
     
       4. The driving circuit as claimed in  claim 2 , wherein the resistive memory element is a metal-insulator-metal element. 
     
     
       5. The driving circuit as claimed in  claim 1 , further comprising a receiver coupled to the node to receive input data via the I/O pad. 
     
     
       6. The driving circuit as claimed in  claim 1 , wherein the output driver is an off-chip driver circuit. 
     
     
       7. The driving circuit as claimed in  claim 1 , wherein the output driver comprises a pull-up driver and a pull-down driver which are respectively controlled by a pull-up driving signal and a pull-down driving signal to control the voltage of the I/O pad.