Optimum current control CMOS cascode amplifier

Abstract

A CMOS cascode amplifier comprises a cascode circuit comprising a plurality of branches in parallel, each branch comprising a first transistor and a second switchable transistor connected in series forming a cascode pair, wherein the cascode circuit is configured to amplify an input signal. The CMOS cascode amplifier further comprises a bias circuit configured to bias the cascode circuit by providing a bias signal to the first transistor in each of the plurality of the branches in the cascode circuit. In addition, the CMOS cascode amplifier comprises a switching control circuit configured to control a quiescent current in the cascode circuit based on selectively activating the plurality of branches by providing a switching control signal that switches on the second switchable transistor in the one or more activated branches.

The invention claimed is: 
     
       1. A CMOS cascode amplifier, comprising:
 a cascode circuit comprising a plurality of branches in parallel, each branch comprising a first transistor and a second switchable transistor connected in series forming a cascode pair, wherein the cascode circuit is configured to amplify an input signal; 
 a bias circuit configured to bias the cascode circuit by providing a bias signal to the first transistor in each of the plurality of the branches in the cascode circuit; and 
 a switching control circuit configured to control a quiescent current in the cascode circuit based on selectively activating the plurality of branches by providing a switching control signal that switches on the second switchable transistor in the one or more activated branches, 
 wherein the cascode pair comprising the first transistor and the second switchable transistor in each of the branches have weighted W/L size. 
 
     
     
       2. The amplifier of  claim 1 , wherein the cascode circuit is further configured to receive the input signal at a gate terminal of the first transistor in each of the plurality of branches of the cascode circuit. 
     
     
       3. The amplifier of  claim 1 , wherein the bias circuit comprises a third transistor configured to form a current mirror with the cascode circuit. 
     
     
       4. The amplifier of  claim 3 , wherein the bias signal is applied to the cascode circuit in order to obtain a predetermined quiescent current in the cascode circuit. 
     
     
       5. The amplifier of  claim 4 , wherein the predetermined quiescent current is obtained by adjusting a reference current in the current mirror circuit. 
     
     
       6. The amplifier of  claim 4 , wherein the predetermined quiescent current is determined based on a total transistor width of the first transistor and the second switchable transistor in each of the plurality of the parallel branches in the cascode circuit. 
     
     
       7. The amplifier of  claim 1 , wherein the switching control circuit comprises a level shifter circuit configured to provide a positive voltage or a negative voltage to a gate terminal of the second switchable transistor based on the switching control signal. 
     
     
       8. A CMOS cascode amplifier, comprising:
 a cascode circuit comprising a plurality of branches in parallel, each branch comprising a first transistor and a second switchable transistor connected in series forming a cascode pair, wherein the cascode circuit is configured to amplify an input signal; 
 a bias circuit configured to bias the cascode circuit by providing a bias signal to the first transistor in each of the plurality of the branches in the cascode circuit; 
 a switching control circuit configured to control a quiescent current in the cascode circuit based on selectively activating the plurality of branches by providing a switching control signal that switches on the second switchable transistor in the one or more activated branches; and 
 an input matching circuit coupled to an input signal path of the cascode circuit configured to tune an input impedance of the cascode circuit, wherein the input matching circuit comprises an input inductance in series with a variable capacitive element comprising a plurality of selectable capacitors. 
 
     
     
       9. The amplifier of  claim 8 , wherein the cascode circuit is further configured to receive the input signal at a gate terminal of the first transistor in each of the plurality of branches of the cascode circuit. 
     
     
       10. The amplifier of  claim 8 , wherein the bias circuit comprises a third transistor configured to form a current mirror with the cascode circuit. 
     
     
       11. The amplifier of  claim 10 , wherein the bias signal is applied to the cascode circuit in order to obtain a predetermined quiescent current in the cascode circuit. 
     
     
       12. The amplifier of  claim 11 , wherein the predetermined quiescent current is obtained by adjusting a reference current in the current mirror circuit. 
     
     
       13. The amplifier of  claim 11 , wherein the predetermined quiescent current is determined based on a total transistor width of the first transistor and the second switchable transistor in each of the plurality of the parallel branches in the cascode circuit. 
     
     
       14. The amplifier of  claim 8 , wherein the switching control circuit comprises a level shifter circuit configured to provide a positive voltage or a negative voltage to a gate terminal of the second switchable transistor based on the switching control signal. 
     
     
       15. The amplifier of  claim 8 , wherein the cascode pair comprising the first transistor and the second switchable transistor in each of the branches have an equal width-to-length (W/L) size. 
     
     
       16. The amplifier of  claim 8 , wherein the cascode pair comprising the first transistor and the second switchable transistor in each of the branches have weighted width-to-length (W/L) size. 
     
     
       17. The amplifier of  claim 8 , wherein the switching control circuit is further configured to selectively activate one or more of the plurality of selectable capacitors based on the switching control signal. 
     
     
       18. A CMOS cascode amplifier, comprising:
 a cascode circuit comprising a plurality of branches in parallel, each branch comprising a first transistor and a second switchable transistor connected in series forming a cascode pair, wherein the cascode circuit is configured to amplify an input signal; 
 a bias circuit configured to bias the cascode circuit by providing a bias signal to the first transistor in each of the plurality of the branches in the cascode circuit; 
 a switching control circuit configured to control a quiescent current in the cascode circuit based on selectively activating the plurality of branches by providing a switching control signal that switches on the second switchable transistor in the one or more activated branches; and 
 a degradation inductance coupled to the cascode circuit configured to adjust a gain of the cascode circuit, the degradation inductance comprising a plurality of taps, each of the taps being coupled to a source terminal of the first transistor of a respective branch. 
 
     
     
       19. The amplifier of  claim 18 , wherein the cascode circuit is further configured to receive the input signal at a gate terminal of the first transistor in each of the plurality of branches of the cascode circuit. 
     
     
       20. The amplifier of  claim 18 , wherein the bias circuit comprises a third transistor configured to form a current mirror with the cascode circuit. 
     
     
       21. The amplifier of  claim 20 , wherein the bias signal is applied to the cascode circuit in order to obtain a predetermined quiescent current in the cascode circuit. 
     
     
       22. The amplifier of  claim 21 , wherein the predetermined quiescent current is obtained by adjusting a reference current in the current mirror circuit. 
     
     
       23. The amplifier of  claim 21 , wherein the predetermined quiescent current is determined based on a total transistor width of the first transistor and the second switchable transistor in each of the plurality of the parallel branches in the cascode circuit. 
     
     
       24. The amplifier of  claim 18 , wherein the cascode pair comprising the first transistor and the second switchable transistor in each of the branches have an equal width-to-length (W/L) size. 
     
     
       25. The amplifier of  claim 17 , wherein the cascode pair comprising the first transistor and the second switchable transistor in each of the branches have weighted width-to-length (W/L) size.