Folding circuit and nonvolatile memory devices

Abstract

A nonvolatile memory device includes a nonvolatile memory cell coupled to a bit line. The nonvolatile memory device may include a sensing circuit configured to output a sensing output signal for sensing a status of the nonvolatile memory cell based on a sensing input signal inputted to the sensing circuit through a sensing input line. The nonvolatile memory device may include a folding circuit coupled to the bit line to output the sensing input signal having a voltage low level or a voltage high level according to a voltage level of the bit line.

What is claimed is: 
     
       1. A nonvolatile memory device comprising:
 a nonvolatile memory cell coupled to a bit line; 
 a sensing circuit configured to output a sensing output signal for sensing a status of the nonvolatile memory cell based on a sensing input signal inputted to the sensing circuit through a sensing input line; and 
 a folding circuit coupled to the bit line to output the sensing input signal having a voltage low level or a voltage high level according to a voltage level of the bit line, 
 wherein the sensing circuit is configured to include a P-MOS transistor and an N-MOS transistor coupled in series between the supply voltage line and a ground voltage, 
 wherein the P-MOS transistor of the sensing circuit has a gate to which an enablement signal is inputted, a source coupled to the supply voltage line, and a drain coupled to the sensing output line; and 
 wherein the N-MOS transistor of the sensing circuit has a gate coupled to the sensing input line, a drain coupled to the sensing output line, and a source coupled to the ground voltage. 
 
     
     
       2. The nonvolatile memory device of  claim 1 , wherein the voltage low level is a ground voltage level, and the voltage high level is substantially a voltage level of the bit line. 
     
     
       3. The nonvolatile memory device of  claim 1 , wherein the nonvolatile memory cell includes a first P-MOS transistor having a floating gate, a source coupled to the bit line, and a drain coupled to a ground voltage, and
 the nonvolatile memory cell further includes a selection transistor coupled between the bit line and the first P-MOS transistor, and 
 wherein the selection transistor is configured to include a second P-MOS transistor having a source coupled to the bit line, a drain coupled to the source of the first P-MOS transistor, and a gate to which a selection enablement signal is inputted. 
 
     
     
       4. The nonvolatile memory device of  claim 1 , further comprising a resistive load portion coupled between the bit line and a supply voltage line,
 wherein the resistive load portion is configured to include a P-MOS transistor having a gate to which the enablement signal is inputted, a source coupled to the supply voltage line, and a drain coupled to the bit line. 
 
     
     
       5. The nonvolatile memory device of  claim 1 ,
 wherein the folding circuit is configured to include a P-MOS transistor and an N-MOS transistor which are coupled in series between the bit line and the ground voltage, 
 wherein the P-MOS transistor of the folding circuit has a gate to which a bias voltage is inputted, a source coupled to the bit line, and a drain coupled to the sensing input line; and 
 wherein the N-MOS transistor of the folding circuit has a gate to which a sense amplification enablement signal is inputted, a drain coupled to the sensing input line, and a source coupled to the ground voltage. 
 
     
     
       6. The nonvolatile memory device of  claim 5 , wherein the enablement signal is an inverted signal of the sense amplification enablement signal. 
     
     
       7. The nonvolatile memory device of  claim 5 , wherein the bias voltage turns off the P-MOS transistor of the folding circuit if the nonvolatile memory cell has a programmed status and turns on the P-MOS transistor of the folding circuit if the nonvolatile memory cell has an initial status. 
     
     
       8. The nonvolatile memory device of  claim 7 ,
 wherein the bias voltage is higher than a voltage that remains after subtracting an absolute value of a threshold voltage of the P-MOS transistor of the folding circuit from a first bit line voltage induced at the bit line when the nonvolatile memory cell has a programmed status; and 
 wherein the bias voltage is equal to or lower than a voltage that remains after subtracting an absolute value of a threshold voltage of the P-MOS transistor of the folding circuit from a second bit line voltage induced at the bit line when the nonvolatile memory cell has an initial status. 
 
     
     
       9. The nonvolatile memory device of  claim 7 , further comprising a bias voltage generator coupled between the supply voltage line and the ground voltage to generate the bias voltage,
 wherein the bias voltage generator includes: 
 a P-MOS transistor and a first resistor coupled in series between the supply voltage line and the gate of the P-MOS transistor of the folding circuit; and 
 a second resistor and a N-MOS transistor coupled in series between the gate of the P-MOS transistor of the folding circuit and the ground voltage. 
 
     
     
       10. The nonvolatile memory device of  claim 9 ,
 wherein a gate of the P-MOS transistor of the bias voltage generator is coupled to a ground voltage, and 
 wherein a gate of the N-MOS transistor of the bias voltage generator is configured to receive the sensing amplification enablement signal. 
 
     
     
       11. A nonvolatile memory device comprising:
 a nonvolatile memory cell coupled to a bit line; 
 a sensing circuit configured to output a sensing output signal for sensing a status of the nonvolatile memory cell based on a sensing input signal inputted to the sensing circuit through a sensing input line; and 
 a folding circuit coupled to the nonvolatile memory cell through the bit line and coupled to the sensing circuit through the sensing input line, 
 wherein the folding circuit prevents a read operation of the nonvolatile memory cell, having a programmed status, from being affected by fluctuation characteristics of transistors within the folding circuit and the sensing circuit, 
 wherein the sensing circuit is configured to include a P-MOS transistor and an N-MOS transistor coupled in series between the supply voltage line and a ground voltage, 
 wherein the P-MOS transistor of the sensing circuit has a gate to which an enablement signal is inputted, a source coupled to the supply voltage line, and a drain coupled to the sensing output line; and 
 wherein the N-MOS transistor of the sensing circuit has a gate coupled to the sensing input line, a drain coupled to the sensing output line, and a source coupled to the ground voltage. 
 
     
     
       12. The nonvolatile memory device according to  claim 11 ,
 wherein the folding circuit prevents the sensing output signal from being affected from a variance in a transconductance of the transistors within the sensing circuit. 
 
     
     
       13. The nonvolatile memory device according to  claim 11 , wherein the effects of the fluctuation characteristics of a first P-MOS transistor of the nonvolatile memory cell having a floating gate, a source coupled to the bit line, and a drain coupled to a ground voltage are prevented by the folding circuit to allow the read operation of the nonvolatile memory cell to be unaffected by the fluctuation characteristics. 
     
     
       14. The nonvolatile memory device according to  claim 11 ,
 wherein the effects of the fluctuation characteristics of the P-MOS transistor and the N-MOS transistor of the sensing circuit are prevented by the folding circuit to allow the read operation of the nonvolatile memory cell to be unaffected by the fluctuation characteristics. 
 
     
     
       15. The nonvolatile memory device according to  claim 11 ,
 wherein the folding circuit is configured to include a third P-MOS transistor and a second N-MOS transistor which are coupled in series between the bit line and a ground voltage, and 
 
       wherein the effects of the fluctuation characteristics of the second N-MOS transistor is prevented by the folding circuit to allow the read operation of the nonvolatile memory cell to be unaffected by the fluctuation characteristics.