Process information extractor circuit

Abstract

A process information extractor circuit includes: a transistor array including a plurality of transistors, and configured such that, among the plurality of transistors, the number of transistors electrically coupled in series is adjusted depending on a code; a current source suitable for adjusting the amount of current flowing through the transistor array to a predetermined value; a comparator suitable for comparing a gate voltage of the transistors electrically coupled in series in the transistor array, with a reference voltage; and a code generator suitable for generating the code according to a comparison result of the comparator.

What is claimed is: 
     
       1. A process information extractor circuit comprising:
 a transistor array including a plurality of transistors having a common gate voltage, and configured such that, among the plurality of transistors, the number of transistors electrically coupled in series is adjusted depending on a code; 
 a current source suitable for adjusting an amount of current flowing through the transistors electrically coupled in series to a predetermined value; 
 a comparator suitable for comparing a reference voltage with the common gate voltage; and 
 a code generator suitable for generating the code according to a comparison result of the comparator. 
 
     
     
       2. The process information extractor circuit according to  claim 1 , wherein the transistors electrically coupled in series have a diode-connected form. 
     
     
       3. The process information extractor circuit according to  claim 2 , wherein the plurality of transistors are PMOS transistors. 
     
     
       4. The process information extractor circuit according to  claim 3 , wherein the current source adjusts the amount of current sunk from the transistors electrically coupled in series to the predetermined value. 
     
     
       5. The process information extractor circuit according to  claim 3 ,
 wherein the code generator generates the code so that the number of transistors electrically coupled in series is increased when the common gate voltage is greater than the reference voltage, and 
 wherein the code generator generates the code so that the number of transistors electrically coupled in series is decreased when the common gate voltage is lower than the reference voltage. 
 
     
     
       6. The process information extractor circuit according to  claim 5 , wherein a value of the code indicates a process information when a difference between the gate voltage and the reference voltage is smallest. 
     
     
       7. The process information extractor circuit according to  claim 2 , wherein the plurality of transistors are NMOS transistors. 
     
     
       8. The process information extractor circuit according to  claim 7 , wherein the current source adjusts the amount of current sourced to the transistors electrically coupled in series to the predetermined value. 
     
     
       9. The process information extractor circuit according to  claim 7 ,
 wherein, when the common gate voltage is greater than the reference voltage, the code generator generates the code such that the number of transistors electrically coupled in series is decreased, and 
 wherein, when the gate voltage is lower than the reference voltage, the code generator generates the code such that the number of transistors electrically coupled in series is increased. 
 
     
     
       10. The process information extractor circuit according to  claim 9 , wherein a value of the code indicates a process information when a difference between the gate voltage and the reference voltage is smallest. 
     
     
       11. An integrated circuit comprising:
 a PMOS transistor array including a plurality of PMOS transistors having a first common gate voltage, and configured such that, among the plurality PMOS transistors, the number of PMOS transistors electrically coupled in series is adjusted depending a first code; 
 a first current source suitable for adjusting an amount of current sunk from the PMOS transistors electrically coupled in series to a first value; 
 a first comparator suitable for comparing a first reference voltage with the first common gate voltage; 
 a first code generator suitable for generating the first code according to a comparison result of the first comparator; 
 an NMOS transistor array including a plurality of NMOS transistors having a second common gate voltage, and configured such that, among the plurality NMOS transistors, the number of NMOS transistors electrically coupled in series is adjusted depending a second code; 
 a second current source suitable for adjusting an amount of current sourced to the NMOS transistors electrically coupled in series to a second value; 
 a second comparator suitable for comparing a second reference voltage with the second common gate voltage; and 
 a second code generator suitable for generating the second code according to a comparison result of the second comparator. 
 
     
     
       12. The integrated circuit according to  claim 11 ,
 wherein the PMOS transistors electrically coupled in series have a diode-connected form, and 
 wherein the NMOS transistors electrically coupled in series have a diode-connected form. 
 
     
     
       13. The integrated circuit according to  claim 11 ,
 wherein, when the first common gate voltage is greater than the first reference voltage, the first code generator generates the first code such that the number of PMOS transistors electrically coupled in series is increased, and 
 wherein, when the first common gate voltage is lower than the first reference voltage, the first code generator generates the first code such that the number of PMOS transistors electrically coupled in series is decreased. 
 
     
     
       14. The integrated circuit according to  claim 11 ,
 wherein, when the second common gate voltage is greater than the second reference voltage, the second code generator generates the second code such that the number of NMOS transistors electrically coupled in series is decreased, and 
 wherein, when the second common gate voltage is lower than the second reference voltage, the second code generator generates the second code such that the number of NMOS transistors electrically coupled in series is increased.