DC blocking circuit with bias control and independent cut-off frequency for AC-coupled circuits

Abstract

A circuit for blocking undesired input direct current of AC-coupled broadband circuits. The circuit includes a capacitor coupled to an input port and a common node. The input port receives a RF input signal. Additionally, the circuit includes a current source supplying a DC current to the common node leading a bias current to an output port. Further, the circuit includes a variable voltage source through an internal load and a close loop with an application circuit having an input load coupled to the output port to determine various bias voltages to control the bias current at the output port in association with a RF output signal that is substantially free of any input direct current originated from the RF input signal and is associated with an inherent low cut-off frequency independent of the various bias voltages.

What is claimed is: 
     
       1. A circuit for blocking undesired input direct current of AC-coupled broadband circuits, the circuit comprising:
 a capacitor having a first plate coupled to an input port and a second plate coupled to a common node, the input port receiving an RF input signal; 
 a current source supplying a DC current to the common node leading a bias current to an output port; 
 a variable voltage source through an internal load forming a close loop with an application circuit having an input load coupled to the output port for determining various bias voltages to control the bias current at the output port in association with a RF output signal that is substantially free of any input direct current originated from the RF input signal and is associated with an inherent low cut-off frequency independent of the various bias voltages. 
 
     
     
       2. The circuit of  claim 1  wherein the low cut-off frequency is determined by capacitance of the capacitor and a parallel combination impedance of the internal load and the input load of the application circuit coupled to the output port and remains a constant as the bias voltages vary in the output port. 
     
     
       3. The circuit of  claim 2  wherein the capacitor is configured to have a reactance based on the capacitance at high frequencies substantially smaller than absolute value of impedance of the input load of the application circuit. 
     
     
       4. The circuit of  claim 1  wherein the internal load is configured to have impedance at high frequencies substantially greater than high frequency impedance of the input load of the application circuit and also have impedance at low frequencies substantially smaller than low frequency impedance of the input load of the application circuit. 
     
     
       5. The circuit of  claim 4  further comprising a high cut-off frequency depended substantially on impedance of the input load of the application circuit. 
     
     
       6. The circuit of  claim 4  wherein the internal load comprises a first load connected to a second load in series for absorbing unwanted portion of the DC current generated by the current source, each of the first load and the second load comprising an arbitrary combination of resistor, capacitor, and inductor with a limitation to have high impedance at high frequencies and low impedance at low frequencies compared to the impedance of the input load of the application circuit. 
     
     
       7. The circuit of  claim 6  further comprising a current controlled current source connected to the first load for absorbing a major percentage ranging from 80% to 90% of the unwanted portion of the DC current to ground substantially independent of the bias voltages set by the variable voltage source. 
     
     
       8. The circuit of  claim 6  wherein the variable voltage source comprises an operational amplifier with low output impedance connected to the second load for substantially absorbing a minor percentage of the unwanted portion of the DC current to ground. 
     
     
       9. The circuit of  claim 8  wherein the operational amplifier is configured to receive a differential input defined by a predetermined reference voltage and a feedback voltage from a close loop including the first load, the second load, through the output port to the input load of the application circuit to yield an output voltage with large gain by substantially reducing the differential input to zero, thereby defining the bias voltage at the output port. 
     
     
       10. The circuit of  claim 1  wherein the input load of the application circuit is an emitter follower made by a bipolar transistor. 
     
     
       11. A method for blocking undesired input direct current of AC-coupled broadband circuits, the method comprising:
 providing a capacitor coupled to an input port and a common node, the input port receiving an RF input signal; 
 providing a DC current to the common node using a current source based on standard power supply, the DC current leading to a bias current at an output port coupled to the common node; 
 connecting an internal load to the common node; 
 providing a variable voltage source to the internal load in a close loop including the output port coupled to an input load of an application circuit for determining various bias voltages to control the bias current; 
 generating an RF output signal in association with the bias current at the output port substantially free from any DC current originally in the RF input signal; and 
 providing a low cut-off frequency associated with the RF output signal independent from the various bias voltages. 
 
     
     
       12. The method of  claim 11  wherein providing a capacitor comprises configuring the capacitor with a reactance at high frequencies substantially smaller than absolute value of impedance of the input load of the application circuit. 
     
     
       13. The method of  claim 12  wherein the low cut-off frequency is determined only by capacitance of the capacitor and impedance of the internal load. 
     
     
       14. The method of  claim 11  wherein the internal load is configured to have impedance at high frequencies substantially greater than high frequency impedance of the input load of the application circuit and also have impedance at low frequencies substantially smaller than low frequency impedance of the input load of the application circuit. 
     
     
       15. The method of  claim 11  further comprising providing a high cut-off frequency depended substantially on impedance of the input load of the application circuit. 
     
     
       16. The method of  claim 11  wherein connecting an internal load comprises connecting a first load to the common node and connecting a second load to the first load in series for absorbing unwanted portion of the DC current generated by the current source, each of the first load and the second load comprising an arbitrary combination of resistor, capacitor, and inductor with an limitation to have high impedance at high frequencies and low impedance at low frequencies compared to the impedance of the input load of the application circuit. 
     
     
       17. The method of  claim 16  further comprising coupling a current controlled current source to the first load for absorbing a major percentage ranging from 80% to 90% of the unwanted portion of the DC current to ground substantially independent of the bias voltages set by the variable voltage source. 
     
     
       18. The method of  claim 16  wherein the variable voltage source comprises an operational amplifier with low output impedance connected to the second load for substantially absorbing a minor percentage of the unwanted portion of the DC current to ground.