Semiconductor device and manufacturing method thereof

Abstract

A fin includes a first region and a second region arranged on a positive side in an X-axis direction with respect to the first region. A control gate electrode covers an upper surface of the first region, and a side surface of the first region on the positive side in a Y-axis direction. A memory gate electrode covers an upper surface of the second region, and a side surface of the second region on the positive side in the Y-axis direction. The upper surface of the second region is lower than the upper surface of the first region. The side surface of the second region is arranged on the negative side in the Y-axis direction with respect to the side surface of the first region in the Y-axis direction.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a semiconductor substrate; 
 a projecting portion serving as a part of the semiconductor substrate, projected from a main surface of the semiconductor substrate, and extending in a first direction when seen in a plan view; 
 a first gate electrode formed over the projecting portion and extending in a second direction intersecting with the first direction when seen in a plan view; 
 a first gate insulating film formed between the first gate electrode and the projecting portion; 
 a second gate electrode formed over the projecting portion, extending in the second direction when seen in a plan view, and adjacent to the first gate electrode; and 
 a second gate insulating film formed between the second gate electrode and the projecting portion and between the second gate electrode and the first gate electrode and including a charge storage unit inside, 
 wherein the projecting portion includes:
 a first region; and 
 a second region arranged on a first side in the first direction with respect to the first region when seen in a plan view, 
 
 wherein the first gate electrode covers a first upper surface of the first region, a first side surface of the first region on a second side in the second direction, and a second side surface of the first region on an opposite side of the second side in the second direction, 
 wherein the second gate electrode covers a second upper surface of the second region, a third side surface of the second region on the second side, and a fourth side surface of the second region on the opposite side of the second side, 
 wherein the second upper surface is lower than the first upper surface, and 
 wherein the third side surface is arranged on the opposite side of the second side with respect to the first side surface in the second direction. 
 
     
     
       2. The semiconductor device according to  claim 1 ,
 wherein a distance between the second upper surface and the first upper surface in a third direction perpendicular to the main surface is longer than a distance between the third side surface and the first side surface in the second direction. 
 
     
     
       3. The semiconductor device according to  claim 1 ,
 wherein the fourth side surface is arranged on the second side with respect to the second side surface in the second direction. 
 
     
     
       4. The semiconductor device according to  claim 3 ,
 wherein a distance between the second upper surface and the first upper surface in a fourth direction perpendicular to the main surface is longer than any of a distance between the third side surface and the first side surface in the second direction and a distance between the fourth side surface and the second side surface in the second direction. 
 
     
     
       5. The semiconductor device according to  claim 1 ,
 wherein the projecting portion includes a third region arranged on an opposite side of the first side with respect to the first region when seen in a plan view, 
 wherein a third upper surface of the third region is lower than the first upper surface and higher than the second upper surface, and 
 wherein a fifth side surface of the third region on the second side is arranged on the opposite side of the second side with respect to the first side surface and is arranged on the second side with respect to the third side surface in the second direction. 
 
     
     
       6. The semiconductor device according to  claim 5 ,
 wherein the fourth side surface is arranged on the second side with respect to the second side surface in the second direction, and 
 wherein a sixth side surface of the third region on the opposite side of the second side is arranged on the second side with respect to the second side surface and is arranged on the opposite side of the second side with respect to the fourth side surface in the second direction. 
 
     
     
       7. The semiconductor device according to  claim 1 ,
 wherein the second gate insulating film includes:
 a first silicon oxide film; 
 a first silicon nitride film on the first silicon oxide film; and 
 a second silicon oxide film on the first silicon nitride film. 
 
 
     
     
       8. The semiconductor device according to  claim 1 ,
 wherein the first gate insulating film, the first gate electrode, the second gate insulating film, and the second gate electrode form a non-volatile memory.