High electron mobility transistor (HEMT)

Abstract

A high electron mobility transistor (HEMT) device with a highly resistive layer co-doped with carbon (C) and a donor-type impurity and a method for making the HEMT device is disclosed. In one embodiment, the HEMT device includes a substrate, the highly resistive layer co-doped with C and the donor-type impurity formed above the substrate, a channel layer formed above the highly resistive layer, and a barrier layer formed above the channel layer. In one embodiment, the highly resistive layer comprises gallium nitride (GaN). In one embodiment, the donor-type impurity is silicon (Si). In another embodiment, the donor-type impurity is oxygen (O).

What is claimed is: 
     
       1. A high electron mobility transistor device comprising:
 a substrate; 
 a highly resistive layer having a lower surface facing the substrate and an upper surface opposing the lower surface, and having a sheet resistance greater than 2300 Ohms/sq formed above the substrate; 
 a channel layer formed above the upper surface of the highly resistive layer; and 
 a barrier layer formed above the channel layer, wherein 
 the highly resistive layer is co-doped with carbon and a donor-type impurity, the donor-type impurity has an average concentration of 5×10 15  atoms/cm 3  or more throughout the resistive layer, a ratio of the average concentration of the donor-type impurity and an average concentration of carbon throughout the resistive layer is greater than 1:1000 and less than 1:1, and a concentration of the donor-type impurity is higher at the upper surface or the lower surface than an average concentration of the donor type impurity from the lower surface to the upper surface. 
 
     
     
       2. The high electron mobility transistor device of  claim 1 , further comprising:
 a source electrode electrically coupled to the barrier layer; 
 a drain electrode electrically coupled to the barrier layer; and 
 a gate electrode electrically coupled to the barrier layer between the source and the drain electrodes. 
 
     
     
       3. The high electron mobility transistor device of  claim 1 , further comprising:
 a buffer layer between the substrate and the highly resistive layer. 
 
     
     
       4. The high electron mobility transistor device of  claim 1 , further comprising:
 a layer of gallium nitride between the substrate and the highly resistive layer. 
 
     
     
       5. The high electron mobility transistor device of  claim 1 , wherein a variance of a concentration of the donor-type impurity is less than 15% throughout the highly resistive layer. 
     
     
       6. The high electron mobility transistor device of  claim 1 , wherein the concentration of the donor-type impurity is higher at the upper surface of the highly resistive layer facing the channel layer than the average concentration of the donor-type impurity throughout the highly resistive layer. 
     
     
       7. The high electron mobility transistor device of  claim 1 , wherein the concentration of the donor-type impurity is higher at the lower surface of the highly resistive layer facing the substrate than the average concentration of the donor-type impurity throughout the highly resistive layer. 
     
     
       8. The high electron mobility transistor device of  claim 1 , wherein the donor-type impurity is silicon. 
     
     
       9. The high electron mobility transistor device of  claim 1 , wherein the donor-type impurity is oxygen. 
     
     
       10. The high electron mobility transistor device of  claim 1 , wherein the highly resistive layer comprises gallium nitride. 
     
     
       11. The high electron mobility transistor device of  claim 1 , wherein the channel layer comprises gallium nitride. 
     
     
       12. The high electron mobility transistor device of  claim 1 , wherein the barrier layer comprises aluminum gallium nitride. 
     
     
       13. The high electron mobility transistor device of  claim 3 , wherein the buffer layer comprises at least one of aluminum gallium nitride and aluminum nitride. 
     
     
       14. The high electron mobility transistor device of  claim 1 , wherein the highly resistive layer has a thickness between 0.25 μm and 6 μm. 
     
     
       15. The high electron mobility transistor device of  claim 1 , wherein the channel layer has a thickness between 120 nm and 4 μm. 
     
     
       16. The high electron mobility transistor device of  claim 3 , wherein the buffer layer has a thickness between 150 Å and 40,000 Å. 
     
     
       17. The high electron mobility transistor device of  claim 12 , wherein the barrier layer has a thickness and a concentration of aluminum corresponding to a charge density in the channel layer between 5.5×10 12  C/cm 2  to 8×10 12  C/cm 2 . 
     
     
       18. A method of forming a high electron mobility transistor device, the method comprising:
 providing a substrate; 
 forming a highly resistive layer co-doped with carbon and a donor-type impurity above the substrate, the highly resistive layer having a lower surface facing the substrate and an upper surface opposing the lower surface, the highly resistive layer having a sheet resistance greater than 2300 Ohms/sq; 
 forming a channel layer above the highly resistive layer; and 
 forming a barrier layer above the channel layer, wherein 
 the donor-type impurity has an average concentration of 5×10 5  atoms/cm 3  or more throughout the highly resistive layer, a ratio of the average concentration of the donor-type impurity and an average concentration of carbon throughout the highly resistive layer is greater than 1:1000 and less than 1:1, and a concentration of the donor-type impurity is higher at the upper surface or the lower surface than an average concentration of the donor type impurity from the lower surface to the upper surface. 
 
     
     
       19. The method of  claim 18 , further comprising:
 forming a source electrode electrically coupled to the barrier layer; 
 forming a drain electrode electrically coupled to the barrier layer; and 
 forming a gate electrode electrically coupled to the barrier layer between the source and drain electrodes. 
 
     
     
       20. The method of  claim 18 , further comprising:
 forming a buffer layer between the substrate and the highly resistive layer. 
 
     
     
       21. The method of  claim 18 , further comprising:
 forming a layer of gallium nitride between the substrate and the highly resistive layer. 
 
     
     
       22. The method of  claim 18 , wherein a variance of a concentration of the donor-type impurity is less than 15% throughout the highly resistive layer. 
     
     
       23. The method of  claim 18 , wherein the concentration of the donor-type impurity is higher at the upper surface of the highly resistive layer facing the channel layer than the average concentration of the donor-type impurity throughout the highly resistive layer. 
     
     
       24. The method of  claim 18 , wherein the concentration of the donor-type impurity is higher at the lower surface of the highly resistive layer facing the substrate than the average concentration of the donor-type impurity throughout the highly resistive layer. 
     
     
       25. The method of  claim 18 , wherein the donor-type impurity is silicon. 
     
     
       26. The method of  claim 18 , wherein the donor-type impurity is oxygen. 
     
     
       27. The method of  claim 18 , wherein the highly resistive layer comprises gallium nitride. 
     
     
       28. The method of  claim 18 , wherein the channel layer comprises gallium nitride. 
     
     
       29. The method of  claim 18 , wherein the barrier layer comprises aluminum gallium nitride. 
     
     
       30. The method of  claim 20 , wherein the buffer layer comprises at least one of aluminum gallium nitride and aluminum nitride. 
     
     
       31. The method of  claim 27 , wherein forming the highly resistive layer co-doped with carbon and the donor-type impurity comprises:
 growing the highly resistive layer in conditions such that carbon incorporation in the gallium nitride is promoted while simultaneously introducing the donor-type impurity. 
 
     
     
       32. The method of  claim 25 , wherein the donor-type impurity is introduced by injecting silane while growing the highly resistive layer. 
     
     
       33. The method of  claim 31 , wherein the growth conditions comprise a low ratio of group V precursors to group III precursors. 
     
     
       34. The method of  claim 33 , wherein the ratio of group V precursors to group III precursors is between 200 and 1400. 
     
     
       35. The method of  claim 31 , wherein the growth conditions comprise growing the highly resistive layer at a pressure between 25 torr and 150 torr. 
     
     
       36. The method of  claim 31 , wherein the growth conditions comprise growing the highly resistive layer at a temperature between 900° C. and 1000° C. 
     
     
       37. The method of  claim 31 , wherein the growth conditions comprise growing the highly resistive layer at a rate between 5 μm/hr and 9 μm/hr. 
     
     
       38. The method of  claim 18 , wherein the highly resistive layer is grown to a thickness between 0.25 μm and 6 μm. 
     
     
       39. The method of  claim 18 , wherein the channel layer is grown to a thickness between 120 nm and 4 μm. 
     
     
       40. The method of  claim 20 , wherein the buffer layer has a thickness between 150 Å and 40,000 Å. 
     
     
       41. The method of  claim 29 , wherein the barrier layer is grown to a thickness and having an aluminum concentration corresponding to a charge density in the channel layer between 5.5×10 12  C/cm 2  to 8×10 12  C/cm 2 .